| Title | Automatic Instrumentation of Embedded Software for High Level Hardware/Software Co-Simulation |
| Author | Aimen Bouchhima, *Patrice Gerin, Frédéric Pétrot (TIMA Laboratory, France) |
| Page | pp. 546 - 551 |
| Keyword | cosimulation, annotation |
| Abstract | We propose an automatic instrumentation method for embedded software annotation to enable performance modeling in high level hardware/software co-simulation environments. The proposed "cross-annotation" technique consists of extending a retargetable compiler infrastructure to allow the automatic instrumentation of embedded software at the basic block level. Thus, target and annotated native binaries are guaranteed to have isomorphic control flow graphs (CFG). The proposed method takes into account the processor-specific optimizations at the compiler level and proves to be accurate with low simulation overhead. |
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| Title | Fast and Accurate Performance Simulation of Embedded Software for MPSoC |
| Author | *Eric Cheung, Harry Hsieh (University of California, Riverside, United States), Felice Balarin (Cadence Design Systems, United States) |
| Page | pp. 552 - 557 |
| Keyword | Performance Simulation, Multiprocessor |
| Abstract | Performance simulation of software for Multiprocessor System-on-a-Chips (MPSoC) suffers from poor tool support. Cycle accurate simulation at Instruction Set Simulation level is too slow and inefficient for any design of realistic size. Behavioral simulation, though useful for functional analysis at high level, does not provide any performance information that is crucial for design and analysis ofMPSoC implementations. As a consequence, designers are often reduced to manually annotate performance information onto behavioral models, which contributes further to inefficiency and inaccuracy. In this paper, we use structural performance models to provide fast and accurate simulation of software for MPSoC.We generate structural models automatically using GCC with accurate performance annotation while considering optimizations for instruction selection, branch prediction, and pipeline interlock. Our structural models are able to simulate at several orders of magnitude faster than ISS and provide less than 1% error on performance estimation. These models allow realistic MPSoC design space explorations based on performance characteristics with simulation speed comparable to behavioral simulation. We validate our simulation models with several benchmarks and demonstrate our approach with a design case study of an MPEG-2 decoder. |
| Title | Automatic Generation of Cycle Accurate and Cycle Count Accurate Transaction Level Bus Models from a Formal Model |
| Author | *Chen Kang Lo, Ren Song Tsay (National Tsing Hua University, Taiwan) |
| Page | pp. 558 - 563 |
| Keyword | System Level Design, Transaction Level Modeling, bus modeling |
| Abstract | This paper proposes the first automatic approach to simultaneously generate Cycle Accurate and Cycle Count Accurate transaction level bus models. Since TLM (Transaction Level Modeling) is proven as an effective design methodology for managing the ever-increasing complexity of system level designs, researchers often exploit various abstraction levels to gain either simulation speed or accuracy. Consequently, designers repeatedly perform the time-consuming task of re-writing and performing consistency checks for different abstraction level models of the same design. To ease the work, we propose a correct-by-construction method that automatically and simultaneously generates both fast and accurate transaction level bus models for system simulation. The proposed approach relieves designers from the tedious and error-prone process of refining models and checking for consistency. |
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| Title | A Combined Analytical and Simulation-Based Model for Performance Evaluation of a Reconfigurable Instruction Set Processor |
| Author | *Farhad Mehdipour (Kyushu University, Japan), Hamid Noori (Institute of Systems, Information Technologies and Nanotechnologies, Japan), Bahman Javadi (Amirkabir University of Technology, Iran), Hiroaki Honda (Institute of Systems, Information Technologies and Nanotechnologies, Japan), Koji Inoue, Kazuaki Murakami (Kyushu University, Japan) |
| Page | pp. 564 - 569 |
| Keyword | Reconfigurable instruction set processors, Analytical modeling, reconfigurable accelerator, Performance evaluation, Design space exploration |
| Abstract | Performance evaluation is a serious challenge in designing or optimizing reconfigurable instruction set processors. The conventional approaches based on synthesis and simulations are very time consuming and need a considerable design effort. A combined analytical and simulation-based model (CAnSOƒx) is proposed and validated for performance evaluation of a typical reconfigurable instruction set processor. The proposed model consists of an analytical core that incorporates statistics gathered from cycle-accurate simulation to make a reasonable evaluation and provide a valuable insight. Compared to cycle-accurate simulation results, CAnSO proves almost 2% variation in the speedup measurement. |
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