(Back to Session Schedule)

The 15th Asia and South Pacific Design Automation Conference

Session 3B  Macromodeling and Verification of Analog Systems
Time: 8:30 - 10:10 Wednesday, January 20, 2010
Location: Room 101B
Chairs: Chin-Fong Chiu (National Chip Implementation Center, Taiwan), Eric Keiter (Sandia National Labs, U.S.A.)

3B-1 (Time: 8:30 - 8:55)
TitleCurrent Source Modeling in the Presence of Body Bias
AuthorSaket Gupta, *Sachin S. Sapatnekar (Univ. of Minnesota, U.S.A.)
Pagepp. 199 - 204
Detailed information (abstract, keywords, etc)
Slides

3B-2 (Time: 8:55 - 9:20)
TitleManifold Construction and Parameterization for Nonlinear Manifold-Based Model Reduction
Author*Chenjie Gu, Jaijeet Roychowdhury (Univ. of California, Berkeley, U.S.A.)
Pagepp. 205 - 210
Detailed information (abstract, keywords, etc)
Slides

3B-3 (Time: 9:20 - 9:45)
TitleA Fast Analog Mismatch Analysis by an Incremental and Stochastic Trajectory Piecewise Linear Macromodel
Author*Hao Yu (Berkeley Design Automation, U.S.A.), Xuexin Liu, Hai Wang, Sheldon Tan (UC Riverside, U.S.A.)
Pagepp. 211 - 216
Detailed information (abstract, keywords, etc)
Slides

3B-4 (Time: 9:45 - 10:10)
TitleFormal Verification of Tunnel Diode Oscillator with Temperature Variations
Author*Kusum Lata, H S Jamadagni (CEDT,Indian Institute of Science, Bangalore, India)
Pagepp. 217 - 222
Detailed information (abstract, keywords, etc)