| Title | A Fast Symbolic Computation Approach to Statistical Analysis of Mesh Networks with Multiple Sources |
| Author | *Zhigang Hao, Guoyong Shi (Shanghai Jiaotong Univ., China) |
| Page | pp. 383 - 388 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | Minimizing Clock Latency Range in Robust Clock Tree Synthesis |
| Author | *Wen-Hao Liu, Yih-Lang Li, Hui-chi Chen (National Chiao Tung Univ., Taiwan) |
| Page | pp. 389 - 394 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | Blockage-Avoiding Buffered Clock-Tree Synthesis for Clock Latency-Range and Skew Minimization |
| Author | *Xin-Wei Shih, Chung-Chun Cheng, Yuan-Kai Ho, Yao-Wen Chang (National Taiwan Univ., Taiwan) |
| Page | pp. 395 - 400 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | Improved Clock-Gating Control Scheme for Transparent Pipeline |
| Author | *Jung Hwan Choi (Samsung Electronics, Republic of Korea), Byung Guk Kim (Purdue Univ., U.S.A.), Aurobindo Dasgupta (Intel Corp., U.S.A.), Kaushik Roy (Purdue Univ., U.S.A.) |
| Page | pp. 401 - 406 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |