| Title | A Dual-MST Approach for Clock Network Synthesis |
| Author | *Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham (The Hong Kong Polytechnic University, Hong Kong), Fung-Yu Young (The Chinese University of Hong Kong, Hong Kong) |
| Page | pp. 467 - 473 |
| Keyword | CNS, CLR |
| Abstract | In nanometer-scale VLSI physical design, clock network becomes a major concern on determining total performance of digital circuit. Clock skew and PVT (Process, Voltage and Temperature) variation contribute a lot to its behavior, and these are the critical issues for clock network synthesis (CNS). Previous works on CNS include delay balancing, geometric matching and link insertion techniques. However, traditional methods mainly focused on skew and wirelength minimization, it may lead to negative influence towards process variation factors. In this paper, a novel clock network synthesizer is proposed and several algorithms are introduced for performance improvement. A dual-MST (DMST) geometric matching approach is proposed for topology construction. It can help balancing the tree structure to reduce the variation effect. A recursive buffer insertion technique and a blockage handling method are also presented, they are developed for proper distribution of buffers and saving of capacitance. Experimental results show that our matching approach is better than the traditional methods, and in particular our synthesizer has better performance compared to the results of the winner in the ISPD 2009 contest. |
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| Title | Buffered Clock Tree Sizing for Skew Minimization Under Power and Thermal Budgets |
| Author | Krit Athikulwongse, *Xin Zhao, Sung Kyu Lim (Georgia Institute of Technology, U.S.A.) |
| Page | pp. 474 - 479 |
| Keyword | clock tree synthesis, low power, thermal budget |
| Abstract | In this paper, we study the clock tree sizing problem for thermal-aware skew minimization under power and thermal budgets. Clock wire/buffer sizing affects not only the delay/skew, but also the power dissipation of the clock tree. This effect in turn triggers changes in thermal distribution, making re-computation of the delay/skew necessary. Thus, the interaction among skew, power, and temperature is highly complicated if tied with clock wire/buffer sizing. In order to efficiently combat the time-varying nature of underlying thermal profile, we focus on two kinds of skew, depending on the number of thermal profiles given: skew value and skew range. The former refers to the skew value computed under a single steady-state thermal profile, while the latter refers to the skew range computed based on multiple thermal profiles. Our thermal-aware sequential-linear-programming approach maintains near-zero skew value and narrow skew range while keeping the power dissipation and temperature under the given budgets. |
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| Title | Critical-PMOS-Aware Clock Tree Design Methodology for Anti-Aging Zero Skew Clock Gating |
| Author | Shih-Hsu Huang, Chia-Ming Chang, *Wen-Pin Tu, Song-Bin Pan (Chung Yuan Christian University, Taiwan) |
| Page | pp. 480 - 485 |
| Keyword | Clock Tree Synthesis, Design for Reliability, Delay Degradation, Clock Skew, Gated Clock Design |
| Abstract | Due to clock gating, the PMOS transistors in the clock tree often have different active probabilities, which lead to different NBTI delay degradations. To ensure that the clock skew is always zero, there is a demand to eliminate the degradation difference. In this paper, we present a critical-PMOS-aware clock tree design methodology to deal with this problem. First, we prove that, under the same tree topology, the NAND-type-matching clock tree has the minimum number of critical PMOS transistors. Then, we propose a 0-1 ILP (integer linear programming) approach to minimize the power consumption overhead while eliminating the degradation difference. Benchmark data consistently show that our design methodology can achieve very good results in terms of both the clock skew (due to the degradation difference) and the power consumption overhead. |
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| Title | Clock Tree Embedding for 3D ICs |
| Author | *Tak-Yung Kim, Taewhan Kim (Seoul National University, Republic of Korea) |
| Page | pp. 486 - 491 |
| Keyword | 3D ICs, clock tree, TSV, routing, optimization |
| Abstract | This paper addresses a fundamental problem of zero skew clock tree embedding problem in 3D ICs. We propose an algorithm, called ZCTE-3D, for solving the zero skew clock tree embedding problem in 3D ICs for a given tree topology. The primary objective is to minimize the cost of TSVs together with finding embedding layers and the secondary objective is to minimize the cost of wirelength. We show that ZCTE-3D solves the problem optimally in polynomial time under the linear delay model, while it solves the problem suboptimally under the Elmore delay model. |
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