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The 15th Asia and South Pacific Design Automation Conference

Session 7B  Power Optimization and Estimation in the DSM Era
Time: 8:30 - 10:10 Thursday, January 21, 2010
Location: Room 101B
Chairs: Kimiyoshi Usami (Shibaura Inst. of Tech., Japan), Masanori Hashimoto (Osaka Univ., Japan)

7B-1 (Time: 8:30 - 8:55)
TitleAn Analytical Dynamic Scaling of Supply Voltage and Body Bias Exploiting Memory Stall Time Variation
Author*Jungsoo Kim, Younghoon Lee (KAIST, Republic of Korea), Sungjoo Yoo (POSTECH, Republic of Korea), Chong-Min Kyung (KAIST, Republic of Korea)
Pagepp. 575 - 580
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7B-2 (Time: 8:55 - 9:20)
TitleBounded Potential Slack: Enabling Time Budgeting for Dual-Vt Allocation of Hierarchical Design
Author*Jun Seomun, Seungwhun Paik, Youngsoo Shin (KAIST, Republic of Korea)
Pagepp. 581 - 586
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7B-3 (Time: 9:20 - 9:45)
TitleDynamic Power Estimation for Deep Submicron Circuits with Process Variation
AuthorQuang Dinh, *Deming Chen, Martin Wong (UIUC, U.S.A.)
Pagepp. 587 - 592
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7B-4 (Time: 9:45 - 10:10)
TitleRuntime Temperature-Based Power Estimation for Optimizing Throughput of Thermal-Constrained Multi-Core Processors
AuthorDongkeun Oh, Nam Sung Kim, Yu Hen Hu (Univ. of Wisconsin, U.S.A.), *Charlie Chung Ping Chen (National Taiwan Univ., Taiwan), Azadeh Davoodi (Univ. of Wisconsin, U.S.A.)
Pagepp. 593 - 599
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