Title | Statistical Timing Verification for Transparently Latched Circuits through Structural Graph Traversal |
Author | *Xingliang Yuan, Jia Wang (Illinois Inst. of Tech., U.S.A.) |
Page | pp. 663 - 668 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A Unified Multi-Corner Multi-Mode Static Timing Analysis Engine |
Author | Jing Jia Nian, *Shih Heng Tsai, Chung Yang (Ric) Huang (National Taiwan Univ., Taiwan) |
Page | pp. 669 - 674 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Statistical Time Borrowing for Pulsed-Latch Circuit Designs |
Author | *Seungwhun Paik, Lee-eun Yu, Youngsoo Shin (KAIST, Republic of Korea) |
Page | pp. 675 - 680 |
Detailed information (abstract, keywords, etc) |
Title | Design Time Body Bias Selection for Parametric Yield Improvement |
Author | *Cheng Zhuo, Yung-Hsu Chang, Dennis Sylvester, David Blaauw (Univ. of Michigan, Ann Arbor, U.S.A.) |
Page | pp. 681 - 688 |
Detailed information (abstract, keywords, etc) |