| Title | Minimizing Leakage Power in Aging-Bounded High-level Synthesis with Design Time Multi-Vth Assignment |
| Author | *Yibo Chen (Penn State Univ., U.S.A.), Yu Wang (Tsinghua Univ., China), Yuan Xie (Penn State Univ., U.S.A.), Andres Takach (Mentor Graphics Corp., U.S.A.) |
| Page | pp. 689 - 694 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Global Interconnect Reduction Technique during High Level Synthesis |
| Author | Taemin Kim (Univ. of California, Los Angeles, U.S.A.), *Xun Liu (North Carolina State Univ., U.S.A.) |
| Page | pp. 695 - 700 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | Incremental High-Level Synthesis |
| Author | Luciano Lavagno (Cadence Design Systems, U.S.A.), Mototsugu Fujii (Renesas Technology Corp., Japan), Alex Kondratyev (Cadence Design Systems, U.S.A.), Noriyasu Nakayama (Fujitsu Advanced Technologies, Japan), Mitsuru Tatesawa (Renesas Technology Corp., Japan), Yosinori Watanabe (Cadence Design Systems, U.S.A.), *Qiang Zhu (Cadence Design Systems, Japan) |
| Page | pp. 701 - 706 |
| Detailed information (abstract, keywords, etc) | |
| Title | A High-Level Synthesis Flow for Custom Instruction Set Extensions for Application-Specific Processors |
| Author | Nagaraju Pothineni (Google, India, India), *Philip Brisk, Paolo Ienne (EPFL, Switzerland), Anshul Kumar, Kolin Paul (Indian Inst. of Tech., Delhi, India) |
| Page | pp. 707 - 712 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |