| Title | High-Density Integration of Functional Modules Using Monolithic 3D-IC Technology |
| Author | *Shreepad Panth (Georgia Institute of Technology, U.S.A.), Kambiz Samadi, Yang Du (Qualcomm Research, U.S.A.), Sung Kyu Lim (Georgia Institute of Technology, U.S.A.) |
| Page | pp. 681 - 686 |
| Keyword | monolithic, power reduction, 3D-IC, floorplanning, block-level design |
| Abstract | Three dimensional integrated circuits (3D-ICs) have emerged as a promising solution to continue device scaling. They can be realized using Through Silicon Vias (TSVs), or monolithic integration using Monolithic Inter-tier vias (MIVs), an emerging alternative that provides much higher via densities. In this paper, we provide a framework for floorplanning existing 2D IP blocks into 3D-ICs using MIVs. We take the floorplanning solution all the way through place and-route and report post-layout metrics for area, wirelength, timing, and power consumption. Results show that the wirelength of TSV-based 3D designs outperform 2D designs by upto 14% in large-scale circuits only. MIV-based 3D designs, however, offer an average wirelength improvement of 33% for a wide range of benchmark circuits. We also show that while TSV-based 3D cannot improve the performance and power unless the TSV capacitance is reduced, MIV-based 3D offers significant reduction of upto 33% in the longest path delay and 35% in the inter-block net power. |
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| Title | Block-level Designs of Die-to-Wafer Bonded 3D ICs and Their Design Quality Tradeoffs |
| Author | *Krit Athikulwongse (Georgia Institute of Technology, U.S.A.), Dae Hyun Kim (Cadence, U.S.A.), Moongon Jung, Sung Kyu Lim (Georgia Institute of Technology, U.S.A.) |
| Page | pp. 687 - 692 |
| Keyword | 3D IC, Block-level Design, Die-to-Wafer Bonding |
| Abstract | In 3D ICs, block-level designs provide various advantages over designs done at other granularity such as gate-level because they promote the reuse of IP blocks. In this paper, we study block-level 3D-IC designs, where the footprint of the dies in the stack are different. This happens in case of die-to-wafer bonding, which is more popular choice for near-term low-cost 3D designs. We study design quality tradeoffs among three different ways to place through-silicon vias (TSVs): TSV-farm, TSV-distributed, and TSV-whitespace. In our holistic approach, we use wirelength, power, performance, temperature, and mechanical stress metrics to conduct comprehensive comparative studies on the three design styles. In addition, we provide analysis on the impact of TSV size and pitch on the design quality of these three styles. |
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| Title | Thermal-reliable 3D Clock-tree Synthesis Considering Nonlinear Electrical-thermal-coupled TSV Model |
| Author | Yang Shang, Chun Zhang, *Hao Yu, Chuan Seng Tan (Nanyang Technological University, Singapore), Xin Zhao, Sung Kyu Lim (Georgia Institute of Technology, U.S.A.) |
| Page | pp. 693 - 698 |
| Keyword | 3D physical design, Clock tree synthesis, Nonlinear electrical-thermal TSV model |
| Abstract | 3D physical design needs accurate model of through-silicon-vias(TSVs). In this paper, physics-based electrical-thermal model is introduced for both signal and dummy thermal TSVs considering nonlinear electrical-thermal dependence. A nonlinear programming-based clock-skew reduction problem is formulated to allocate thermal TSVs for clock-skew reduction under non-uniform temperature distribution. Experiments show that under the nonlinear electrical-thermal TSV model, insertion of thermal TSVs can effectively reduce temperature-gradient introduced clock-skew by 58.4% on average which is 11.6% higher than the result under linear electrical-thermal model. |
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| Title | Stacking Signal TSV for Thermal Dissipation in Global Routing for 3D IC |
| Author | *Po-Yang Hsu, Hsien-Te Chen, TingTing Hwang (National Tsing Hua University, Taiwan) |
| Page | pp. 699 - 704 |
| Keyword | 3D IC, stacked TSV |
| Abstract | With no further shrink of device size, three dimensional (3D) chip stacking by Through-Silicon-VIA (TSV) has been identified as an effective way to achieve better performance in speed and power. However, such solution inevitably encounters challenges in thermal dissipation since stacked dies generate significant amount of heat per unit volume. We leverage an integrated architecture of stacked-signal-TSVs to minimize temperature with small wiring overhead. Based on the structure of stacked signal TSV, a two-stage TSV locating algorithm in global routing is designed. By this TSV locating algorithm, we demonstrate that our stacking signal TSV structure is able to reduce 17% temperature with 4% wiring overhead and 3% performance loss calculated by 3D Elmore delay model. Compared to a previous work by Cong and Zhang [1] where additional thermal TSVs are inserted, our experimental results have in average 23% less TSVs than Cong and Zhang’s [1] with the same temperature constraint. |
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