Designers' Forum is conceived as a unique program that shares the design experience and solutions of real product developments among LSI designers and EDA academia/developers. The topics discussed in this forum include heterogeneous device integration, photonics for embedded systems, embedded GPUs, and hardware-software co-design/verification.
- Date: January 24-25, 2013
- Place: Pacifico Yokohama, Conference Center, 4F, Room 411+412
- Designers' Forum Chair: Yoshio Masubuchi (Toshiba Corp., Japan)
- Designers' Forum Chair: Koji Inoue (Kyushu University, Japan)
|5A||January 24 / 13:40 - 15:40||Oral Session:
Heterogeneous Devices and Multi-Dimensional Integration Design Technologies
|6A||January 24 / 16:00 - 18:00||Panel Discussion:
Future Direction and Trend of Embedded GPU
|8A||January 25 / 13:40 - 15:40||Oral Session:
Photonics for Embedded Systems
|9A||January 25 / 16:00 - 18:00||Panel Discussion:
Harmonized Hardware-Software Co-design and Co-verification
Session 5A: Thursday, January 24, 13:40-15:40, Room 411+412
Oral Session: Heterogeneous Devices and Multi-Dimensional Integration Design Technologies
Organizer: Akihiko Okubora (Sony Corp., Japan)
Recently 2.5D/3D integration is getting hot technology area as one of the solutions for "Beyond Moore". However, the design technology is still not mature to achieve cost effective and best performed LSIs. In this session the design issues and solutions will be presented and the things to do will be discussed for future.
- 1: Heterogeneous 3D Integration
Kazuya Masu (Tokyo Institute of Technology, Japan)
- 2: 3DIC from Concept to Reality
Frank Lee, Bill Shen, Willy Chen and Suk Lee (Taiwan Semiconductor Manufacturing Company, Ltd., Taiwan)
3DIC technology presents a new system integration strategy for the industry to achieve superior system performance with lower power consumption, higer bandwidth, smaller system form factor, and shorter time to market through heterogeneous integration. TSMC's "Chip-on-Wafer-on-Substrate (CoWoS)" technology opens up the new opportunity to bring the 3DIC vision from concept to reality. The presentation will be talking about this market trend and the different pieces needed to jointly make it a success, which includes customers' killer applications, TSMC's process technology, as well as the ecosystem design enablement of multi-die implementation, verification, test and new categories of IPs.
- 3: 2.5D Design Methodology
Sinya Tokunaga (Semiconductor Technology Academic Research Center (STARC), Japan)
STARC is developing to realize the state of the art technology of the 3D-IC design integrity with Co-design and Co-analysis called "Cool Chip" Project. The "Cool Chip" project is made up of 3 projects System Design, Mix-Signal, and Multi-Chip Co-Design project. The Multi-Chip design project focuses on developing a 2.5D co-design environment for consumer products. We present the new issues of initiating fusion of LSI technology with package technology using 2.5D design methodology. Especially, very important issue is a high frequency insertion loss on the silicon interposer.
- 4: Design Issues in Heterogeneous 3D/2.5D Integration
Dragomir Milojevic, Pol Marchal, Erik Jan Marinissen, Geert Van der Plas, Diederik Verkest and Eric Beyne (IMEC, Belgium)
Efficient processing of fine pitched Through Silicon Vias, micro-bumps and back side re-distribution layers enable face-to-back or face-to-face integration of heterogeneous ICs using 3D stacking and/or Silicon Interposers. While these technology features are extremely compelling, they considerably stress the existing design practices and EDA tool flows, typically conceived for 2D systems. With all system, technology and implementation level options brought with these features, design space increases to an extent where traditional 2D tools cannot be used any more for efficient exploration. Therefore, the cost-effective design of future 3D ICs products will require new planning and co-optimization techniques and tools that are fast and accurate enough to cope with these challenges. In this paper we present design methodology and practical EDA tool chain that covers different aspects of the design flow and are specific to efficient design of 3D-ICs. Flow features include: fast synthesis and 3D design partitioning at gate level, TSV/micro-bump array planning, 3D floor planning, placement and routing, congestion analysis, fast thermal and mechanical modeling, easy technology vs. implementation trade-off analysis, 3D device models generation and design-for-test (DfT). The application of the tool chain is illustrated using concrete examples of real world designs, showing not only the applicability of the tool chain, but also the benefits of heterogeneous 2.5 and 3D integration technologies.
Session 6A: Thursday, January 24, 16:00-18:00, Room 411+412
Panel Discussion: Future Direction and Trend of Embedded GPU
Organizer: Masaitsu Nakajima (Panasonic Corp., Japan)
In SoC designs for mobile and home applications, GPU is one of the key components to differentiate their products. Panelists from major embedded GPU IP companies will introduce their own GPU technology, feature, development strategy, and future trend. This panel discusses which direction we should go to and what will be next killer applications for future GPUs.
|Moderator:||Koji Inoue (Kyushu University, Japan)|
Jem Davies (ARM Fellow and VP Technology from Media Processing Division, ARM Ltd., UK)
Hong Jiang (Intel's Chief Media Architect and Intel Fellow, Intel Corp., USA)
Eisaku Ohbuchi (Director, Digital Media Professionals Inc., Japan)
Yasushi Sugama (Researcher, Fujitsu Laboratories Ltd., Japan)
Tony King-Smith (VP Marketing Technology Division, Imagination Technologies Ltd., UK)
Session 8A: Friday, January 25, 13:40-15:40, Room 411+412
Oral Session: Photonics for Embedded Systems
Organizer: Yong Lee (Hitachi, Ltd., Japan)
For long time, optical interconnect has been considered as a successor of high-speed electrical interconnection and compound-semiconductor-based optical interconnects have been introduced into telecom optical network and HPC (high performance computing) applications. Recently, Silicon-photonics-based optical interconnect has become commercial and is expected to be an inexpensive, lower power and ultra high bandwidth solution. This session includes four papers about the first silicon-photonics-based commercial AOC (Active Optical Cable) and its design methodology, a high-speed photo detecting circuit, a low-voltage optical transceiver and a silicon-photonics-based optical switch. This session can be a hint for embedded system designers to introduce an optical interconnect into their products.
- 1: Silicon Photonics Technology Platform for Embedded and Integrated Optical Interconnect Systems
Peter De Dobbelaere (Luxtera Inc., USA)
The talk will address: Semiconductor process and packaging technology, Design environment: Electro-Optic design kit for the technology, Application of the technology for a 4 x 28 G transceiver, and Roadmap towards fully integrated photonics with ASICs (switches, CPU, FPGA).
- 2: High-frequency circuit design for 25Gb/s×4 Optical Transceiver
Norio Chujo (Hitachi, Ltd., Japan)
A 25 Gb/s optical transceiver module has been developed for backplane. An optical transceiver for backplane is necessary to downsize current modules while achieving a low power and a high speed up to 25 Gb/s. To realize it, we employ many approaches: crosstalk noise reduction, power integrity enhancement, CMOS-based analog FE, on-chip termination and optical waveform optimization. The fully integrated transceiver IC was fabricated in the 65-nm CMOS process and the package is small, being 9 X 14 mm^2 in size. We measured the output signal of the transceiver and obtained good eye-opening at 25 Gb/s.
- 3: Design and application of highly integrated optical switches based on silicon photonics
Shigeru Nakamura (NEC Corp., Japan)
Novel optical switches based on silicon photonics have been developed for optical access network. Design methodology and measurement results are detailed. This optical switch has advantages of power and footprint, and further applications will be discussed.
- 4: High Performance PIN Ge Photodetector and Si Optical Modulator with MOS Junction for Photonics-Electronics Convergence System
Junichi Fujikata (PETRA, Japan)
Session 9A: Friday, January 25, 16:00-18:00, Room 411+412
Panel Discussion: Harmonized Hardware-Software Co-design and Co-verification
Organizer: Nobuyuki Nishiguchi (Cadence Design Systems, Japan)
LSI applications become much wider in sensor networks, mobiles, auto motives, health cares and various types of electrical devices. Therefore system designs including hardware-software co-design and co-verification for those devices are keys and much important. This may be an old statement since 1990's, however we believe that the system design is now in the new step. On the other hand, is that turned to the same direction that a designer's request, the strategy of a tool vendor, and the interest object of academic research? The panelists form tool vender, semiconductor company, and university who will discuss these subject.
|Moderator:||Koichiro Yamashita (Research manager, Fujitsu Laboratories Ltd., Japan)|
Atsushi Ike (Research manager, Fujitsu Laboratories Ltd., Japan)
Hiroyuki Ikegami (Manager, Renesas Electronics Corp., Japan)
Tsuyoshi Isshiki (Associate Professor, Tokyo Institute of Technology, Japan)
Rainer Leupers (Professor, RWTH Aachen, Germany)
Yosinori Watanabe (Senior Architect, Cadence Berkeley Labs., USA)
Tim Kogel (Solution Architect, Synopsys, Inc., USA)