| Title | Efficient Synthesis of Quantum Circuits Implementing Clifford Group Operations |
| Author | *Philipp Niemann (University of Bremen, Germany), Robert Wille (University of Bremen/Cyber Physical Systems DFKI GmbH/Technical University Dresden, Germany), Rolf Drechsler (University of Bremen/Cyber Physical Systems DFKI GmbH, Germany) |
| Page | pp. 483 - 488 |
| Keyword | quantum circuits, synthesis, Clifford groups, stabilizer circuits |
| Abstract | Quantum circuits established themselves as a promising emerging technology and, hence, attracted significant attention in the domain of computer-aided design. As a result, many approaches for synthesis of corresponding netlists have been proposed in the last decade. However, as the design of quantum circuits poses significant obstacles caused by phenomena such as superposition, entanglement, and phase shifts, automatic synthesis still represents a significant challenge. In this paper, we propose an automatic synthesis approach for quantum circuits that implement Clifford Group operations. These circuits constitute an important subclass of quantum computation and cover core aspects of quantum functionality. The proposed approach exploits specific properties of the unitary transformation matrices that are associated to each quantum operation. Furthermore, Quantum Multiple-Valued Decision Diagrams (QMDDs) are employed for an efficient representation of these matrices. Experimental results confirm that this enables a compact realization of the respective quantum functionality. |
| Slides |
| Title | Optimal SWAP Gate Insertion for Nearest Neighbor Quantum Circuits |
| Author | *Robert Wille (University of Bremen/Cyber Physical Systems DFKI GmbH/Technical University Dresden, Germany), Aaron Lye (University of Bremen, Germany), Rolf Drechsler (University of Bremen/Cyber Physical Systems DFKI GmbH, Germany) |
| Page | pp. 489 - 494 |
| Keyword | quantum circuits, optimization, nearest neighbor, synthesis |
| Abstract | Motivated by its promising applications e.g. for database search or factorization, significant progress has been made in the development of automated design methods for quantum circuits. But in order to keep up with recent physical developments in this domain, new technological constraints have to be considered. Limited interaction distance between gate qubits is one of the most common of these constraints. This led to the development of several strategies aiming at making a given quantum circuit nearest neighbor-complying by adding SWAP gates into the existing circuit structure. However, all of these strategies are of heuristic nature. In this work, we present an exact approach that enables nearest neighbor compliance by adding a minimal number of SWAP gates. Experiments demonstrate the efficiency of the approach. |
| Slides |
| Title | Qubit Placement to Minimize Communication Overhead in 2D Quantum Architectures |
| Author | Alireza Shafaei, Mehdi Saeedi, *Massoud Pedram (University of Southern California, U.S.A.) |
| Page | pp. 495 - 500 |
| Keyword | Quantum Computing, Qubit Placement, 2D Quantum Architectures, Interaction Distance |
| Abstract | Regular, local-neighbor topologies of quantum architectures restrict interactions to adjacent qubits, which in turn increases the latency of quantum circuits mapped to these architectures. To alleviate this effect, optimization methods that consider qubit-to-qubit interactions in 2D grid architectures are presented in this paper. The proposed approaches benefit from Mixed Integer Programming (MIP) formulation for the qubit placement problem. Simulation results on various benchmarks show 27% on average reduction in communication overhead between qubits compared to best results of previous work. |
| Slides |
| Title | A Novel Wirelength-Driven Packing Algorithm for FPGAs with Adaptive Logic Modules |
| Author | Sheng-Kai Wu, *Po-Yi Hsu, Wai-Kei Mak (National Tsing Hua University, Taiwan) |
| Page | pp. 501 - 506 |
| Keyword | FPGA, packing, clustering, ALM |
| Abstract | Adaptive logic module (ALM) in modern field programmable
gate array can serve as one 6-input lookup table
(LUT) or two smaller lookup tables under certain constraints.
In a typical design flow, a netlist of LUTs formed after technology
mapping has to be merged into ALMs and then packed into
coarse-grained logic blocks (CLBs) before placement and routing.
How the LUTs are merged and the ALMs are packed has
a significant impact on the quality of the placement. We propose
a novel wirelength-driven algorithm to merge the LUTs and
pack the ALMs to ensure that it will not adversely affect the final
wirelength. Experimental results show that substituting AAPack
[7] by our algorithm yields about 14.69% reduction in number
of tracks and 16.83% wirelength improvement for ALM-based
FPGA. Applying our algorithm to traditional FPGA, the minimum
number of tracks and wirelength are reduced by 16.32%
and 17.90%, respectively, compared to T-VPack. |
| Slides |