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The 21st Asia and South Pacific Design Automation Conference

Session 2A  Advances in Verification
Time: 13:50 - 15:30 Tuesday, January 26, 2016
Location: TF4203
Chairs: Jason C. Verley (Sandia National Labs, U.S.A.), Zuochang Ye (Tsinghua Univ., China)

2A-1 (Time: 13:50 - 14:15)
TitleAutomatic Abstraction Refinement of TR for PDR
AuthorKuan Fan, *Ming-Jen Yang, Chung-Yang (Ric) Huang (National Taiwan Univ., Taiwan)
Pagepp. 121 - 126
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2A-2 (Time: 14:15 - 14:40)
TitleA Complete Approach to Unreachable State Diagnosability via Property Directed Reachability
Author*Ryan Berryhill, Andreas Veneris (Univ. of Toronto, Canada)
Pagepp. 127 - 132
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2A-3 (Time: 14:40 - 15:05)
TitleFormally Analyzing Fault Tolerance in Datapath Designs using Equivalence Checking
AuthorPayman Behnam (Univ. of Tehran, Iran), Bijan Alizadeh (Univ. of Tehran, and IPM, Iran), Sajjad Taheri (Univ. of Tehran, Iran), *Masahiro Fujita (Univ. of Tokyo, Japan)
Pagepp. 133 - 138
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2A-4 (Time: 15:05 - 15:30)
TitleCoupling Reverse Engineering and SAT to Tackle NP-Complete Arithmetic Circuitry Verification in ~O(# of gates)
Author*Yi Diao, Xing Wei (Easy-Logic Technology, Hong Kong), Tak.Kei Lam (Chinese Univ. of Hong Kong, Hong Kong), Yu.Liang Wu (Easy-Logic Technology, Hong Kong)
Pagepp. 139 - 146
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