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The 16th Asia and South Pacific Design Automation Conference

Session 1C  Advances in Model Order Reduction and Extraction Techniques
Time: 10:20 - 12:20 Wednesday, January 26, 2011
Location: Room 414+415
Chairs: Sheldon X.-D. Tan (University of California, Riverside, U.S.A.), Genichi Tanaka (Renesas, Japan)

1C-1 (Time: 10:20 - 10:50)
TitleA Moment-Matching Scheme for the Passivity-Preserving Model Order Reduction of Indefinite Descriptor Systems with Possible Polynomial Parts
Author*Zheng Zhang (Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, U.S.A.), Qing Wang, Ngai Wong (Department of Electrical and Electronic Engineering, the University of Hong Kong, Hong Kong), Luca Daniel (Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, U.S.A.)
Pagepp. 49 - 54
Keywordmodel order reduction, indefinite descriptor system, system passivity, polynomial part
AbstractPassivity-preserving model order reduction (MOR) of descriptor systems (DSs) is highly desired in the simulation of VLSI interconnects and on-chip passives. One popular method is PRIMA, a Krylov-subspace projection approach which preserves the passivity of positive semidefinite (PSD) structured DSs. However, system passivity is not guaranteed by PRIMA when the system is indefinite. Furthermore, the possible polynomial parts of singular systems are normally not captured. For indefinite DSs, positive-real balanced truncation (PRBT) can generate passive reduced-order models (ROMs), whose main bottleneck lies in solving the dual expensive generalized algebraic Riccati equations (GAREs). This paper presents a novel moment-matching MOR for indefinite DSs, which preserves both the system passivity and, if present, also the improper polynomial part. This method only requires solving one GARE, therefore it is cheaper than existing PRBT schemes. On the other hand, the proposed algorithm is capable of preserving the passivity of indefinite DSs, which is not guaranteed by traditional moment-matching MORs. Examples are finally presented showing that our method is superior to PRIMA in terms of accuracy.
Slides

1C-2 (Time: 10:50 - 11:20)
TitleBalanced Truncation for Time-Delay Systems Via Approximate Gramians
Author*Xiang Wang, Qing Wang, Zheng Zhang, Quan Chen, Ngai Wong (The University of Hong Kong, Hong Kong)
Pagepp. 55 - 60
Keywordmodel reduction, balanced truncation, time-delay systems
AbstractIn circuit simulation, when a large RLC network is connected with delay elements, such as transmission lines, the resulting system is a time-delay system (TDS). This paper presents a new model order reduction (MOR) scheme for TDSs with state time delays. It is the first time to reduce a TDS using balanced truncation. The Lyapunov-type equations for TDSs are derived, and an analysis of their computational complexity is presented. To reduce the computational cost, we approximate the controllability and observability Gramians in the frequency domain. The reduced-order models (ROMs) are then obtained by balancing and truncating the approximate Gramians. Numerical examples are presented to verify the accuracy and efficiency of the proposed algorithm.
Slides

1C-3 (Time: 11:20 - 11:50)
TitleEfficient Sensitivity-Based Capacitance Modeling for Systematic and Random Geometric Variations
AuthorYu Bi (Delft University of Technology, Netherlands), Pieter Harpe (Holst Centre/IMEC, Netherlands), *Nick van der Meijs (Delft University of Technology, Netherlands)
Pagepp. 61 - 66
Keywordprocess variations, capacitance, sensitivity, Design-for-Manufacturability
AbstractThis paper presents a highly efficient sensitivity-based method for capacitance extraction, which models both systematic and random geometric variations. With only one system solve, the nominal capacitances as well as its relative standard deviations caused by both variations can be obtained, at a very modest additional computational time which is negligible compared to that of the standard capacitance extraction without considering any variation. Specifically, experiments and a case study have been analyzed to show the impact of the random variation on the capacitance for a real design.
Slides

1C-4 (Time: 11:50 - 12:20)
TitleParallel Statistical Capacitance Extraction of On-Chip Interconnects with an Improved Geometric Variation Model
Author*Wenjian Yu, Chao Hu (Tsinghua University, China), Wangyang Zhang (Carnegie Mellon University, U.S.A.)
Pagepp. 67 - 72
Keywordcapacitance extraction, random variation, parallel computing, geometric modeling
AbstractIn this paper, a new geometric variation model, referred to as the improved continuous surface variation (ICSV) model, is proposed to accurately imitate the random variation of on-chip interconnects. In addition, we implemented a new statistical capacitance solver which incorporates the ICSV model, the weighted PFA [6] and HPC [5] techniques. The solver also employs a parallel computing technique to greatly improve its efficiency. Experiments show that on a typical 65nm technology structure, ICSV model has significant advantage over other existing models, and the new solver is at least 10X faster than the MC simulation with 10000 samples. The parallel solver achieves 7X further speedup on an 8-core machine. We conclude this paper with several criteria to discuss the trade-off between different geometric models and statistical methods for different scenarios.
Slides