| Title | Equivalent Lumped Element Models for Various n-Port Through Silicon Vias Networks |
| Author | *Khaled Salah Mohamed (Mentor Graphics, Egypt), Hani Ragai (Ain-Shams University, Egypt), Yehea Ismail (Nile University, Egypt), Alaa El Rouby (Mentor Graphics, Egypt) |
| Page | pp. 176 - 183 |
| Keyword | Three-Dimensional ICs, Through Silicon Via, Dimensional Analysis., TSV, Modeling |
| Abstract | This paper proposes an equivalent lumped element
model for various multi-TSV arrangements and introduces
closed form expressions for the capacitive, resistive, and
inductive coupling between those arrangements. The closed form
expressions are in terms of physical dimensions and material
properties and are driven based on the dimensional analysis
method. The model’s compactness and compatibility with SPICE
simulators allows the electrical modeling of various TSV
arrangements without the need for computationally expensive
field-solvers and the fast investigation of a TSV impact on a 3-D
circuit performance. The proposed model accuracy is tested
versus a detailed electromagnetic simulation and showed less
than 6% difference. Finally, the proposed model can be a
possible solution to the industrial need for broadband electrical
modeling of TSVs interconnections arising in 3-D integration.
Also, our presented work provides valuable insight into creating
guidelines for TSV macro-modeling. |
| Slides |
| Title | Clock Tree Optimization for Electromagnetic Compatibility (EMC) |
| Author | *Xuchu Hu, Matthew R. Guthaus (University of California, Santa Cruz, U.S.A.) |
| Page | pp. 184 - 189 |
| Keyword | EMC, Clock, Dynamic programming |
| Abstract | Electromagnetic Interference (EMI) generated by electronic systems is increasing with operating frequency and shrinking process technologies. The clock distribution network is one of the major causes of on-chip EMI. In this paper, we discuss the EMI problem in clock tree design. Spectrum analysis shows that slew rate of clock signal is the main parameter determining the high-frequency spectral content distribution. This is the first work to consider maximum and minimum buffer slew rates in clock tree synthesis to reduce EMI. In this paper, we propose a dynamic programming algorithm to optimize the clock tree considering both traditional metrics and Electromagnetic Compatibility (EMC). Our experimental results show that slew can be controlled in a feasible range and high-frequency spectrum contents can be reduced without sacrificing the traditional metrics such as power and skew. With the efficient optimization and pruning method, the biggest benchmark which has 1728 sinks is able to complete in four minutes. |
| Slides |
| Title | Pulser Gating: A Clock Gating of Pulsed-Latch Circuits |
| Author | *Sangmin Kim, Inhak Han, Seungwhun Paik, Youngsoo Shin (Korea Advanced Institute of Science and Technology, Republic of Korea) |
| Page | pp. 190 - 195 |
| Keyword | Pulsed-latch, sequential circuit, clock gating, low power |
| Abstract | A pulsed-latch is an ideal sequencing element for low-power ASIC designs due to its smaller capacitance and simple timing model. Clock gating of pulsed-latch circuits can be realized by gating a pulse generator (or pulser), which we call pulser gating. The problem of pulser gating synthesis is formulated for the first time. A heuristic algorithm that considers all three factors (similarity of gating functions, literal count to implement gating functions, and proximity of latches) is proposed. |
| Slides |