| Title | OPAL: A Multi-Layer Hybrid Photonic NoC for 3D ICs |
| Author | *Sudeep Pasricha, Shirish Bahirat (Colorado State University, U.S.A.) |
| Page | pp. 345 - 350 |
| Keyword | photonic interconnects, networks on chip, chip multiprocessors, 3D ICs |
| Abstract | Three-dimensional integrated circuits (3D ICs) offer a significant opportunity to enhance the performance of emerging chip multiprocessors (CMPs) using high density stacked device integration and shorter through silicon via (TSV) interconnects that can alleviate some of the problems associated with interconnect scaling. In this paper we propose and explore a novel multi-layer hybrid photonic NoC fabric (OPAL) for 3D ICs. Our proposed hybrid photonic 3D NoC combines low cost photonic rings on multiple photonic layers with a 3D mesh NoC in active layers to significantly reduce on-chip communication power dissipation and packet latency. OPAL also supports dynamic reconfiguration to adapt to changing runtime traffic requirements, and uncover further opportunities for reduction in power dissipation. Our experimental results and comparisons with traditional 2D NoCs, 3D NoCs, and previously proposed hybrid photonic NoCs (photonic Torus, Corona, Firefly) indicate a strong motivation for considering OPAL for future 3D ICs as it can provide orders of magnitude reduction in power dissipation and packet latencies. |
| Title | Enabling Quality-of-Service in Nanophotonic Network-on-Chip |
| Author | *Jin Ouyang, Yuan Xie (The Pennsylvania State University, U.S.A.) |
| Page | pp. 351 - 356 |
| Keyword | optical interconnect, network-on-chip, quality-of-service |
| Abstract | With the recent development in silicon photonics, researchers have developed optical network-on-chip (NoC) architectures that achieve both low latency and low power, which are beneficial for future large scale chip-multiprocessors (CMP). However, none of the existing optical NoC architectures has quality-of-service (QoS) support, which is a desired feature of an efficient interconnection network. QoS support provides contending flows with differentiated bandwidths according to their priorities (or weights), which is crucial to account for application-specific communication patterns and provides bandwidth guarantees for real-time applications.
In this paper, we propose a quality-of-service framework for optical network-on-chip based on frame-based arbitration. We show that the proposed approach achieves excellent differentiated bandwidth allocation with only simple hardware additions and low performance overheads. To the best of our knowledge, this is the first work that provides QoS support for optical network-on-chip. |
| Slides |
| Title | Vertical Interconnects Squeezing in Symmetric 3D Mesh Network-on-Chip |
| Author | *Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li (Institute of Computing Technology, Chinese Academy of Sciences, China) |
| Page | pp. 357 - 362 |
| Keyword | 3D, Network-on-Chip, Mesh, Through silicon via |
| Abstract | Three-dimensional (3D) integration and Network-on-Chip (NoC) are both proposed to tackle the on-chip interconnect scaling problems, and extensive research efforts have been devoted to the design challenges of combining both. Through-silicon via (TSV) is considered to be the most promising technology for 3D integration, however, TSV pads distributed across planar layers occupy significant chip area and result in routing congestions. In addition, the yield of 3D integrated circuits decreased dramatically as the number of TSVs increases. For symmetric 3D mesh NoC, we observe that the TSVs’ utilization is pretty low and adjacent routers rarely transmit packets via their vertical channels (i.e. TSVs) at the same time. Based on this observation, we propose a novel TSV squeezing scheme to share TSVs among neighboring router in a time division multiplex mode, which greatly improves the utilization of TSVs. Experimental results show that the proposed method can save significant TSV footprint with negligible performance overhead. |
| Slides |
| Title | Power-efficient Tree-based Multicast Support for Networks-on-Chip |
| Author | *Wenmin Hu (School of Computer, National University of Defense Technology, China), Zhonghai Lu, Axel Jantsch (Royal Institute of Technology, Sweden), Hengzhu Liu (School of Computer, National University of Defense Technology, China) |
| Page | pp. 363 - 368 |
| Keyword | NoC, multicast, power-efficient |
| Abstract | In this paper, a novel hardware supporting for multicast on mesh Networks-on-Chip (NoC) is proposed. It supports multicast routing on any shape of tree-based path. Two power-efficient tree-based multicast routing algorithms, Optimized tree(OPT) and Left-XY-Right-Optimized tree (LXYROPT) are also proposed. Compared with baseline, OPT and LXYROPT achieve a remarkable improvement both in latency and throughput while reducing the power consumption. |
| Slides |