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The 16th Asia and South Pacific Design Automation Conference

Session 4C  Architecture Design and Reliability
Time: 10:20 - 12:20 Thursday, January 27, 2011
Location: Room 414+415
Chairs: Shigeru Yamashita (Ritsumeikan Univ., Japan), Rolf Drechsler (Univ. of Bremen, Germany)

4C-1 (Time: 10:20 - 10:50)
TitleArea-Efficient FPGA Logic Elements: Architecture and Synthesis
Author*Jason Anderson (Univ. of Toronto, Canada), Qiang Wang (Xilinx, Inc., U.S.A.)
Pagepp. 369 - 375
Detailed information (abstract, keywords, etc)

4C-2 (Time: 10:50 - 11:20)
TitleSelectively Patterned Masks: Structured ASIC with Asymptotically ASIC Performance
Author*Donkyu Baek, Insup Shin, Seungwhun Paik, Youngsoo Shin (KAIST, Republic of Korea)
Pagepp. 376 - 381
Detailed information (abstract, keywords, etc)

4C-3 (Time: 11:20 - 11:50)
TitleA Robust ECO Engine by Resource-Constraint-Aware Technology Mapping and Incremental Routing Optimization
Author*Shao-Lun Huang, Chi-An Wu, Kai-Fu Tang, Chang-Hong Hsu, Chung-Yang (Ric) Huang (National Taiwan Univ., Taiwan)
Pagepp. 382 - 387
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4C-4 (Time: 11:50 - 12:20)
TitleSETmap: A Soft Error Tolerant Mapping Algorithm for FPGA Designs with Low Power
AuthorChi-Chen Peng, Chen Dong, *Deming Chen (Univ. of Illinois, Urbana-Champaign, U.S.A.)
Pagepp. 388 - 393
Detailed information (abstract, keywords, etc)