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The 16th Asia and South Pacific Design Automation Conference

Session 6B  Clock Network Design
Time: 16:00 - 18:00 Thursday, January 27, 2011
Location: Room 413
Chairs: Yuchun Ma (Tsinghua Univ., China), Youngsoo Shin (KAIST, Republic of Korea)

6B-1 (Time: 16:00 - 16:30)
TitleAn Optimal Algorithm for Allocation, Placement, and Delay Assignment of Adjustable Delay Buffers for Clock Skew Minimization in Multi-Voltage Mode Designs
Author*Kyoung-Hwan Lim, Taewhan Kim (Seoul National Univ., Republic of Korea)
Pagepp. 503 - 508
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6B-2 (Time: 16:30 - 17:00)
TitleOn Applying Erroneous Clock Gating Conditions to Further Cut Down Power
Author*Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yu-Liang Wu (Chinese Univ. of Hong Kong, Hong Kong)
Pagepp. 509 - 514
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6B-3 (Time: 17:00 - 17:30)
TitleLow Power Discrete Voltage Assignment Under Clock Skew Scheduling
AuthorLi Li (Northwestern Univ., U.S.A.), Jian Sun (Fudan Univ., China), Yinghai Lu, *Hai Zhou (Northwestern Univ., U.S.A.), Xuan Zeng (Fudan Univ., China)
Pagepp. 515 - 520
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6B-4 (Time: 17:30 - 18:00)
TitleA Practical Method for Multi-domain Clock Skew Optimization
Author*Yanling Zhi (Fudan Univ., China), Hai Zhou (Northwestern Univ., U.S.A.), Xuan Zeng (Fudan Univ., China)
Pagepp. 521 - 526
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