Title | An Optimal Algorithm for Allocation, Placement, and Delay Assignment of Adjustable Delay Buffers for Clock Skew Minimization in Multi-Voltage Mode Designs |
Author | *Kyoung-Hwan Lim, Taewhan Kim (Seoul National Univ., Republic of Korea) |
Page | pp. 503 - 508 |
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Title | On Applying Erroneous Clock Gating Conditions to Further Cut Down Power |
Author | *Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yu-Liang Wu (Chinese Univ. of Hong Kong, Hong Kong) |
Page | pp. 509 - 514 |
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Title | Low Power Discrete Voltage Assignment Under Clock Skew Scheduling |
Author | Li Li (Northwestern Univ., U.S.A.), Jian Sun (Fudan Univ., China), Yinghai Lu, *Hai Zhou (Northwestern Univ., U.S.A.), Xuan Zeng (Fudan Univ., China) |
Page | pp. 515 - 520 |
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Title | A Practical Method for Multi-domain Clock Skew Optimization |
Author | *Yanling Zhi (Fudan Univ., China), Hai Zhou (Northwestern Univ., U.S.A.), Xuan Zeng (Fudan Univ., China) |
Page | pp. 521 - 526 |
Detailed information (abstract, keywords, etc) | |
Slides |