| Title | Robust Spatial Correlation Extraction with Limited Sample via L1-Norm Penalty |
| Author | Mingzhi Gao, *Zuochang Ye, Dajie Zeng, Yan Wang, Zhiping Yu (Institute of Microelectronics, Tsinghua University, China) |
| Page | pp. 677 - 682 |
| Keyword | process variation, spatial correlation, kriging model, L1 regularization, least angle regression |
| Abstract | Random process variations are often composed of location dependent part and distance dependent correlated part. While an accurate extraction of process variation is a prerequisite of both process improvement and circuit performance prediction, it is not an easy task to characterize such complicated spatial random process from a limited number of silicon data. For this purpose, kriging model was introduced to silicon society. This work forms a modified kriging model with L1-norm penalty which offers improved robustness. With the help of Least Angle Regression (LAR) in solving a
core optimization sub-problem, this model can be characterized efficiently.
Some promising results are presented with numerical experiments where
a 3X improvement in model accuracy is shown. |
| Slides |
| Title | Device-Parameter Estimation with On-chip Variation Sensors Considering Random Variability |
| Author | *Ken-ichi Shinkai, Masanori Hashimoto (Osaka University, Japan) |
| Page | pp. 683 - 688 |
| Keyword | variation sensor, device-parameter extraction, process variability, die-to-die variation, within-die variation |
| Abstract | Device-parameter monitoring sensors inside a chip are gaining its importance as the post-fabrication tuning is becoming of a practical use.
In estimation of variational parameters using on-chip sensors, it is often assumed that the outputs of variation sensors are not affected by random variations.
However, random variations can deteriorate the accuracy of the estimation result.
In this paper, we propose a device-parameter estimation method with on-chip variation sensors explicitly considering random variability.
The proposed method derives the global variation parameters and the standard deviation of the random variability using the maximum likelihood estimation.
We experimentally verified that the proposed method can accurately estimate variations,
whereas the estimation result deteriorates when neglecting random variations.
We also demonstrate an application result of the proposed method to test chips fabricated in a 65-nm process technology. |
| Slides |
| Title | Accounting for Inherent Circuit Resilience and Process Variations in Analyzing Gate Oxide Reliability |
| Author | Jianxin Fang, *Sachin S. Sapatnekar (Department of ECE, University of Minnesota, U.S.A.) |
| Page | pp. 689 - 694 |
| Keyword | Oxide Breakdown, Reliability Analysis, Process Variation |
| Abstract | Gate oxide breakdown is a major cause of reliability failures in future nanometer-scale CMOS designs. This paper develops an analysis technique that can predict the probability of a functional failure in a large digital circuit due to this phenomenon. Novel features of the method include its ability to account for the inherent resilience in a circuit to a breakdown event, while simultaneously considering the impact of process variations. Based on standard process variation models, at a specified time instant, this procedure determines the circuit failure probability as a lognormal distribution. Experimental results demonstrate this approach is accurate compared with Monte Carlo simulation, and gives 4.7-5.9x better lifetime prediction over existing methods that are based on pessimistic area-scaling models. |
| Title | Variation-Tolerant and Self-Repair Design Methodology for Low Temperature Polycrystalline Silicon Liquid Crystal and Organic Light Emitting Diode Displays |
| Author | *Chih-Hsiang Ho, Chao Lu, Debabrata Mohapatra, Kaushik Roy (ECE, Purdue University, U.S.A.) |
| Page | pp. 695 - 700 |
| Keyword | LTPS, LCD, OLED, Two-cycle, Variation |
| Abstract | In low temperature polycrystalline silicon (LTPS) based display technologies, the electrical parameter variations in thin film transistors (TFTs) caused by random grain boundaries (GBs) result in significant yield loss, thereby impeding its wide deployment. In this paper, from a system and circuit design perspective, we propose a new self-repair design methodology to compensate the GB-induced variations for LTPS liquid crystal displays (LCDs) and active-matrix organic light emitting diode (AMOLED) displays. The key idea is to extend the charging time for detected low drivability pixel switches, hence, suppressing the brightness non-uniformity and eliminating the need for large voltage margins. The proposed circuit was implemented in VGA LCD panels which were used for prediction of power consumption and yield. Based on the simulation results, the proposed circuit decreases the required supply voltage by 20% without performance and yield degradation. 7% yield enhancement is observed for high resolution, large sized LCDs while incurring negligible power penalty. This technique enables LTPS-based displays either to further scale down the device size for higher integration and lower power consumption or to have superior yield in large sized panels with small power overhead. |
| Slides |