| Title | A Physical-Location-Aware Fault Redistribution for Maximum IR-Drop Reduction |
| Author | *Fu-Wei Chen, Shih-Liang Chen, Yung-Sheng Lin, TingTing Hwang (National Tsing Hua University, Taiwan) |
| Page | pp. 701 - 706 |
| Keyword | delay fault test, at-speed testing, IR-drop |
| Abstract | To guarantee that an application specific integrated circuits (ASIC) meets its timing requirement, at-speed scan testing becomes an indispensable procedure for verifying the performance of ASIC. However, at-speed scan test suffers the test-induced yield loss. Because the switching activity in test mode is much higher than that in normal mode, the switching-induced large current drawn causes severe IR drop and increases gate delay. X-filling is the most commonly used technique to reduce IRdrop effect during at-speed test. However, the effectiveness of X-filling depends on the number and the characteristic of X-bit distribution. In this paper, we propose a physical-location-aware X-identification which re-distributes faults so that the maximum switching activity is guaranteed to be reduced after X-filling. The experimental results on ITC’99 show that our method has an average of 8.54% more reduction of maximum IR-drop as compared to a previous work which re-distributes X-bits evenly in all test vectors. |
| Slides | |
| Title | On the Impact of Gate Oxide Degradation on SRAM Dynamic and Static Write-ability |
| Author | *Vikas Chandra, Robert Aitken (ARM, U.S.A.) |
| Page | pp. 707 - 712 |
| Keyword | Reliability, Gate oxide degradation, SRAM, Vmin |
| Abstract | Low voltage operation of SRAM arrays is critical in reducing the power consumption of embedded microprocessors. The minimum voltage of operation, Vmin, can be limited by any combination of write failure, read disturb failure, access failure and/or retention failure. Of these, the write failure is often observed as the major Vmin limiter in sub-50nm processes. In addition, the current generation transistors have high-k metal gate (HKMG) and these are prone to degradation due to higher level of electric field stress. The degradation increases Vmin due to increase in dynamic write failures and eventually, static write failures as the supply voltage decreases. We show that there exists a critical breakdown resistance (Rcrit) for a given supply voltage at which the SRAM write failure transitions from being dynamically limited to statically limited. For a 32nm low-power SRAM, the value of Rcrit increases by ∼9X as the supply voltage reduces from 1V to 0.7V. Further, we show that the commonly used SRAM write assist (WA) techniques do not lower Rcrit and can only improve the write-ability when the breakdown resistance, Rsbd, is larger than Rcrit. |
| Title | A Self-Testing and Calibration Method for Embedded Successive Approximation Register ADC |
| Author | Xuan-Lun Huang, Ping-Ying Kang (National Taiwan University, Taiwan), Hsiu-Ming Chang (University of California, Santa Barbara, U.S.A.), *Jiun-Lang Huang (National Taiwan University, Taiwan), Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai, Cheng-Wen Wu (Industrial Technology Research Institute, Taiwan) |
| Page | pp. 713 - 718 |
| Keyword | mixed-signal testing, ADC testing, ADC calibration, SoC testing, successive approximation register (SAR) ADC |
| Abstract | This paper presents a self-testing and calibration method for the embedded successive approximation register (SAR) analog-to-digital converter (ADC). We first propose a low cost design-for-test (DfT) technique which tests a SAR ADC by characterizing its digital-to-analog converter (DAC) capacitor array. Utilizing DAC major carrier transition testing, the required analog measurement range is just 4 LSBs; this significantly lowers the test circuitry complexity. We also develop a fully-digital missing code calibration technique that utilizes the proposed testing scheme to collect the required calibration information. Simulation results are presented to validate the proposed technique. |
| Slides | |
| Title | On-chip Dynamic Signal Sequence Slicing for Efficient Post-Silicon Debugging |
| Author | *Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita (The University of Tokyo, Japan) |
| Page | pp. 719 - 724 |
| Keyword | Post-Silicon debugging, Functional Debugging, Dependency Analysis |
| Abstract | In post-silicon debugging, low observability of internal signal values and large amount of traces are considered as the most critical problems. To address these problems, we propose an on-chip circuitry named DSC (Dynamic Slicing Circuit) which outputs the input signal values that actually influence on an erroneous output value in a particular execution of a chip by analyzing dependencies among signals. Since such input signal values are usually a small subset of the entire input sequence, we can reproduce the error by simulation using them. To realize DSC, we propose a variable named d-tag (Dependency Tag) representing dependency of a signal value with respect to another signal value. For demonstrating our method, we prepared three design examples and implemented DSC circuits on them. As a result, we could successfully extract input signal values that influenced the target output value from a number of random input sequence, for every case. We observed that the number of the extracted input values was significantly smaller than that of the original sequence. The area overhead for DSC circuit were also practical, 4% in average. |
| Slides | |