| Title | Fault Simulation and Test Generation for Clock Delay Faults |
| Author | *Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi (Ehime University, Japan), Kewal K. Saluja (University of Wisconsin-Madison, U.S.A.) |
| Page | pp. 799 - 805 |
| Keyword | Test generation, Fault simulation, Delay faults, LSI testing |
| Abstract | In this paper, we investigate the effects of delay faults on clock lines under launch-on-capture test strategy.
We first show simulation results providing a relation between the duration of the delay and difficulty of detecting such faults in the launch-on-capture test.
Next, we propose test generation methods to detect such clock delay faults, and show some experimental results to establish the effectiveness of our methods. |
| Slides |
| Title | Compression-Aware Capture Power Reduction for At-Speed Testing |
| Author | *Jia Li (Tsinghua University, China), Qiang Xu (The Chinese University of Hong Kong, Hong Kong), Dong Xiang (Tsinghua University, China) |
| Page | pp. 806 - 811 |
| Keyword | low power testing, test compression, co-optimization, at-speed testing |
| Abstract | Test compression has become a de facto technique in VLSI testing. Meanwhile, excessive capture power of at-speed testing has also become a serious concern. Therefore, it is important to co-optimize test power and compression ratio in at-speed testing. In this
paper, a novel X-filling framework is proposed to reduce capture power of at-speed testing for different test compression schemes. The proposed technology has been validated by the experimental results on larger ITC'99 benchmark circuits. |
| Slides |
| Title | Fault Diagnosis Aware ATE Assisted Test Response Compaction |
| Author | Joseph Howard, *Sudhakar M Reddy (University of Iowa, U.S.A.), Irith Pomeranz (Purdue University, U.S.A.), Bernd Becker (University of Freiburg, Germany) |
| Page | pp. 812 - 817 |
| Keyword | Diagnosis, Test response compaction, ATE assisted, Direct diagnosis, Multiple faults |
| Abstract | Recently a new method called ATE assisted compaction for achieving test response compaction has been proposed. The method relies on testers to achieve additional compaction, without compromising fault coverage, beyond what may already be achieved using on-chip response compactors. The method does not add additional logic or modify the circuit under test or require additional tests and thus can be used with any design including legacy designs. In this work, we enhance this method so that the level of diagnostic resolution achieved without it can be maintained. Experimental results on larger ISCAS-89 show that additional test response compaction can be achieved while diagnostic resolution for single and double stuck-at faults is not adversely impacted by the procedure. |
| Slides |
| Title | Secure Scan Design Using Shift Register Equivalents against Differential Behavior Attack |
| Author | *Hideo Fujiwara (Nara Institute of Science and Technology, Japan), Katsuya Fujiwara, Hideo Tamamoto (Akita University, Japan) |
| Page | pp. 818 - 823 |
| Keyword | Design for testability, Scan design, Security, Testability, Scan-based side-channel attack |
| Abstract | In this paper, we consider a scan-based side-channel attack called differential-behavior attack and propose several classes of SR-equivalent scan circuits using dummy flip-flops in order to protect the scan-based differential-behavior attack. To show the security level of those extended scan circuits, we introduce differential-behavior equivalent relation, and clarify the number of SR-equivalent extended scan circuits, the number of differential-behavior equivalent classes and the cardinality of those equivalent classes. |
| Slides |