| Title | An Efficient Algorithm of Adjustable Delay Buffer Insertion for Clock Skew Minimization in Multiple Dynamic Supply Voltage Designs |
| Author | Kuan-Yu Lin, *Hong-Ting Lin, Tsung-Yi Ho (National Cheng Kung University, Taiwan) |
| Page | pp. 825 - 830 |
| Keyword | Clock Skew Minimization, Power Mode, Multiple Dynamic Supply Voltage, Adjustable Delay Buffer, Post-Silicon Tuning |
| Abstract | Power consumption is known to be a crucial issue in current IC designs. To tackle this problem, multiple dynamic supply voltage (MDSV) designs are proposed as an efficient solution in modern IC designs. However, the increasing variability of clock skew during the switching of power modes leads to an increase in the complication of clock skew reduction in MDSV designs. In this paper, we propose a tunable clock tree structure by adopting the adjustable delay buffers (ADBs). The ADBs can be used to produce additional delays, hence the clock latencies and skew become tunable in a clock tree. Importing a buffered clock tree, the ADBs with delay value assignments are inserted to reduce clock skew in MDSV designs. An efficient algorithm of ADB insertion for the minimization of clock skew, area, and runtime in MDSV designs has been presented. Comparing with the state-of-the-art algorithm, experimental results show maximum 42.40% area overhead improvement and 117.84x runtime speedup. |
| Slides |
| Title | An Integer Programming Placement Approach to FPGA Clock Power Reduction |
| Author | *Alireza Rakhshanfar, Jason Anderson (University of Toronto, Canada) |
| Page | pp. 831 - 836 |
| Keyword | FPGAs, power, placement, ILP, clock signals |
| Abstract | Clock signals are responsible for a significant portion
of dynamic power in FPGAs owing to their high toggle frequency
and capacitance. Clock signals are distributed to loads
through a programmable routing tree network, designed to provide
low delay and low skew. The placement step of the FPGA
CAD flow plays a key role in influencing clock power, as clock tree
branches are connected based solely on the placement of the clock
loads. In this paper, we present a placement-based approach to
clock power reduction based on an integer linear programming
(ILP) formulation. Our technique is intended to be used as an optimization post-pass executed after traditional placement, and it
offers fine-grained control of the amount by which clock power is
optimized versus other placement criteria. Results show that the
proposed technique reduces clock network capacitance by over
50% with minimal deleterious impact on post-routed wirelength
and circuit speed. |
| Slides |
| Title | Row-Based Area-Array I/O Design Planning in Concurrent Chip-Package Design Flow |
| Author | Ren-Jie Lee, *Hung-Ming Chen (National Chiao Tung University, Taiwan) |
| Page | pp. 837 - 842 |
| Keyword | Area-Array IC Design, Preliminary I/O-Bump Planning, Chip-Package Feasibility Study |
| Abstract | IC-centric design flow has been a common paradigm when designing and optimizing a system. Package and board/system designs are usually followed by almost-ready chip designs, which causes long turn-around time communicating with package and system houses. In this paper, the realizations of areaarray I/O design methodologies are studied. Different from IC-centric flow, we propose a chip-package concurrent design flow to speed up the design time. Along with the flow, we design the I/O-bump (and P/G-bump) tile which combines I/O (and P/G)
and bump into a hard macro with the considerations of I/O power connection and electrostatic discharge (ESD) protection. We then employ an I/O-row based scheme to place I/O-bump tiles with existed metal layers. By such a scheme, it reduces efforts in I/O placement legalization and the redistribution layer (RDL) routing. With the emphasis on package design awareness, the proposed methods map package balls onto chip I/Os, thus providing an opportunity to design chip and package in parallel. Due to this early study of I/O and bump planning, faster convergence can be expected with concurrent design flow. The results are encouraging and the merits of this flow are reassuring. |
| Slides |
| Title | A Provably Good Approximation Algorithm for Rectangle Escape Problem with Application to PCB Routing |
| Author | Qiang Ma, Hui Kong, *Martin D. F. Wong (University of Illinois at Urbana-Champaign, U.S.A.), Evangeline F. Y. Young (The Chinese University of Hong Kong, Hong Kong) |
| Page | pp. 843 - 848 |
| Keyword | PCB Routing, NP Complete, Approximation, Algorithm |
| Abstract | In this paper, we introduce and study the Rectangle Escape Problem
(REP) which is motivated by PCB bus escape routing. Given a rectangular region R and a set S of rectangles within R, REP is to choose a direction for each rectangle to escape to the boundary of R, such that the resultant maximum density over R is minimized. We prove that REP is NP-Complete, and show that REP can be formulated as an Integer Linear Program (ILP). A provably good approximation algorithm for REP is developed by applying Linear Programming (LP) relaxation and a special rounding technique to the ILP. This approximation algorithm is also shown to work for a more general version of REP with weights (Weighted REP). In addition, an iterative refinement procedure is proposed as a postprocessing step to further improve the results. Our approach is tested on a set of industrial PCB bus escape routing problems. Experimental results show that the optimal solution can be obtained within 3 seconds for each of the test cases. |
| Slides |