The 17th Asia and South Pacific Design Automation Conference
Technical Program

Remark: The presenter of each paper is marked with "*".

Technical Program: SIMPLE version DETAILED version with abstract One Page (Not Separated) version

Author Index: HERE

Session Schedule

Monday, January 30, 2012

Tuesday, January 31, 2012

Room 204A	Room 204B	Room 203	Room 202
1K (Room 204A+204B) Opening & Keynote 1 8:30 - 9:50
Coffee Break 9:50 - 10:20
2K (Room 204A+204B) Keynote 2 10:20 - 11:10
3K (Room 204A+204B) Keynote 3 11:10 - 12:00
Lunch 12:00 - 14:00
S1 Special Session 1: Robust and Resilient Designs from the Bottom-Up: Technology, CAD, Circuit, and System Issues 14:00 - 15:40	1A Architecture Issues in Embedded Systems 14:00 - 15:40	1B Power Network Design and Analysis 14:00 - 15:40	1C Emerging Circuits and Memories 14:00 - 15:40
Coffee Break 15:40 - 16:10
S2 Special Session 2: Domain Specific Accelerators 16:10 - 17:50	2A System-Level Optimization Techniques for Multi-Core Architectures 16:10 - 17:50	2B High-Speed PCB Routing 16:10 - 17:50	2C Emerging Test Solutions 16:10 - 17:50

Wednesday, February 1, 2012

Room 204A	Room 204B	Room 203	Room 202
I1 (Room 204A) Invited Talk 1 8:30 - 9:20
I2 (Room 204A) Invited Talk 2 9:20 - 10:10
Coffee Break 10:10 - 10:40
S3 Special Session 3: Design and Prototyping of Invasive MPSoC Architectures 10:40 - 12:20	S4 Special Session 4: Making ESL Models Work 10:40 - 12:20	3B High-Level Synthesis 10:40 - 12:20	3C Yield and Manufacturability Enhancement 10:40 - 12:20
Lunch 12:20 - 14:00
S5 Special Session 5: Advanced Post-silicon Validation and Debugging Techniques for SoC 14:00 - 15:40	S6 Special Session 6: Design and Architecture of Emerging Non-volatile Memory Technologies 14:00 - 15:40	4B 3D IC Layout 14:00 - 15:40	4C Simulation and Modeling for Signal-Integrity Analysis 14:00 - 15:40
Coffee Break 15:40 - 16:10
S7 Special Session 7: Sensor Node Optimization in Machine-to-Machine (M2M) Networks 16:10 - 17:50	5A Adaptive and Power-Efficient NoC Architectures 16:10 - 17:25	5B Physical Optimization for Power and Timing 16:10 - 17:50	5C Parallelizing System-Level Simulation 16:10 - 17:25

Thursday, February 2, 2012

Room 204A	Room 204B	Room 203	Room 202
D1 University LSI Design Contest 1 8:30 - 10:10	6A Efficient Methods for Resource Utilization in Multi-Core NoC Designs 8:30 - 10:10	6B Circuit-Level Timing Optimization 8:30 - 10:10	6C Modeling and Simulation for Nanoscale Analog Circuits 8:30 - 10:10
Coffee Break 10:10 - 10:40
D2 University LSI Design Contest 2 10:40 - 12:20	7A System-Level Modeling, Simulation, and Verification 10:40 - 12:20	7B Timing, Thermal, and Power Issues in High-Performance Design 10:40 - 12:20	7C Interconnect, Cooling, and Charge Storage Technologies 10:40 - 12:20
Lunch 12:20 - 14:00
S8 Special Session 8: Design for Reconfigurability and Adaptivity: Device, Circuit and System Perspectives 14:00 - 15:40	8A Scheduling for Embedded and High-Performance Systems 14:00 - 15:40	8B Automated Debugging and Validation 14:00 - 15:40	8C DFM for Nanolithography 14:00 - 15:40
Coffee Break 15:40 - 16:10
S9 Special Session 9: Quality Assurance for 3D-Stacked ICs 16:10 - 17:50	9A Design for System Reliability 16:10 - 17:50	9B Logic and Datapath Synthesis 16:10 - 17:50	9C Video, Display, and Signal Processing Technologies and Techniques 16:10 - 17:50