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チュートリアル
各分野の第一人者が、システムレベルからデバイスレベルまで、基礎から現場で役立つ実践まで最新技術を伝授します。企業でのマルチコアアプリケーション開発、チップ設計、ＣＡＤ開発、アナログ設計をされている方、また大学や企業でチップ設計やＣＡＤの研究をされている方等に必ずお役に立つ情報です。また、様々な技術の融合した分野の入門的内容も用意していますので、新たな分野を拓こうとしている方にも最適です。新着!! ASP-DAC 2013では、従来のHalf-day料金で３種類のトピックを聴講できる大変お得な システムを導入しました。受講者は5種類のトピック(各2時間)から3種類を自由に選択できます。
- 日時：2013年1月22日(火) (9:30 - 17:30)
- 場所：パシフィコ横浜, 会議場4階
| Room 416+417 | Room 414+415 | Room 413 | Room 411+412 | |
| 9:30 - 11:30 | チュートリアル-1 組込みマルチプロセッサシステム向けプログラミング：アプリケーションコードマッピングと性能見積もり技術 |
チュートリアル-2 パルスベース設計とその最適化 |
チュートリアル-4 不揮発性メモリに基づく設計 |
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| 13:00 - 15:00 | チュートリアル-1 組込みマルチプロセッサシステム向けプログラミング：アプリケーションコードマッピングと性能見積もり技術 |
チュートリアル-3 温度とプロセスばらつきを考慮したディペンダブル組込みシステム |
チュートリアル-4 不揮発性メモリに基づく設計 |
チュートリアル-5 RF CMOS＆MEMS回路設計入門 |
| 15:30 - 17:30 | チュートリアル-2 パルスベース設計とその最適化 |
チュートリアル-3 温度とプロセスばらつきを考慮したディペンダブル組込みシステム |
チュートリアル-5 RF CMOS＆MEMS回路設計入門 |
(学生グループ割引: 同じ所属の4人以上の学生が対象)
| 早期割引 (円) | 正規 (円) | |
| 会員 | 22,000 | 26,000 |
| 非会員 | 26,000 | 30,000 |
| 学生 | 14,000 | 16,000 |
| 学生グループ割引 | 10,000 | 12,000 |
チュートリアル-1: 1月22日(火), 9:30 - 11:30, 13:00 - 15:00@Room 416+417
組込みマルチプロセッサシステム向けプログラミング：アプリケーションコードマッピングと性能見積もり技術
- オーガナイザ:
- Prof. Rainer Leupers (RWTH Aachen University, Germany)
- 講師:
- Prof. Rainer Leupers (RWTH Aachen University, Germany)
- Prof. Tsuyoshi Isshiki (Tokyo Institute of Technology, Japan)
概要:
The trend towards multicore, and even manycore, hardware platforms is a great revolution in the embedded computing industry. In particular, efficient mapping of applications to MPSoC´s is a highly challenging task. For many embedded application domains, MPSoCs have evolved to complex systems, providing homogeneous and heterogeneous processing elements next to multi-level memory hierarchies. This mix of hardware facilities is needed to obtain the required processing speed and power efficiency, but makes a system hard to implement from the application programmer perspective.This tutorial discusses the major challenges and state-of-the-art solution approaches in embedded MPSoC programming. It covers DSP oriented programming models and languages, spatial/temporal task mapping and scheduling techniques, as well as optimized parallel code generation. The first part focuses on novel compilation technologies in the MAPS ("MPSoC Application Programming Studio") compiler. MAPS is based on a lightweight C language extension (CPN, C for Process Networks) that allows for modeling parallel applications, while simultaneously allowing to preserve investments in sequential legacy code. It will be demonstrated how MAPS is capable of generating efficient parallel code for heterogeneous platforms like the TI OMAP DSP family. Performance estimation is a key component of any MPSoC code generator. Therefore, the second part of the tutorial focuses on fast MPSoC system performance estimation technique using trace-driven workload simulation. This framework is capable of estimating application execution cycles with near cycle-accuracy while keeping the workload simulation time comparable to that of native SW executions. Various MPSoC components (buses, memories, processors, etc.) can be parameterized to allow efficient architecture exploration as well as optimizing MPSoC applications for a fixed MPSoC platform.
チュートリアル-2: 1月22日(火), 9:30 - 11:30@Room 414+415, 15:30 - 17:30@Room 416+417
パルスベース設計とその最適化
- オーガナイザ:
- Prof. Youngsoo Shin (Korea Advanced Institute of Science and Technology, Korea)
- 講師:
- Prof. Youngsoo Shin (Korea Advanced Institute of Science and Technology, Korea)
概要:
With severe clocking overhead with increasing clock frequency, there is a demand for faster sequencing element even in ASIC design. A pulsed-latch is a good candidate to serve this demand; it is faster, tolerates some amount of clock skew, and allows some degree of time borrowing. We review how pulsed-latch is deployed in ASIC synthesis flow and which CAD problems should be addressed. The issues that will be covered include the application of sequential optimization techniques (e.g. time borrowing, clock skew scheduling, and retiming) to pulsed-latch circuits and efficient fix of hold violations; pulse generator insertion and application of clock gating; placement and clock tree synthesis.Pulse can conveniently be used to create a dual edge-triggered flip-flop (DETFF), which helps reduce clock power consumption and simplify clock network of multiple clock domain. Design issues regarding DETFF circuits, including timing analysis and clock gating, are addressed. Logic synthesis potential by employing DETFFs is also presented.
チュートリアル-3: 1月22日(火), 13:00 - 15:00, 15:30 - 17:30@Room 414+415
温度とプロセスばらつきを考慮したディペンダブル組込みシステム
- オーガナイザ:
- Prof. Anand Raghunathan (Purdue University, USA)
- 講師:
- Prof. Jörg Henkel (Karlsruhe Institute of Technology, Germany)
- Prof. Nikil Dutt (University of California, Irvine, USA)
概要:
Embedded systems are increasingly becoming susceptible to a host of errors that affect both functional and non-functional aspects of their behavior as we aggressively scale down to nano-technology nodes. This poses significant challenges for the design of dependable embedded systems. The tutorial covers two important drivers - temperature and process variation - that degrade the dependability of embedded systems, and discusses possible mechanisms to ameliorate their negative impacts.In the first part of the tutorial, we cover basics of on-chip reliability from a thermal point of view i.e., how heat/temperature is related to reliability. We introduce the concepts of NBTI and Electromigration etc., and make the case that many reliability-related mechanisms are accelerated by temperature. Since temperature is important, we also discuss challenges posed by, and solutions for how to estimate and measure temperature. We conclude the first part of the tutorial by giving hints on how to control on-chip temperature through mechanisms such as load balancing.
In the second part of the tutorial, we review causes of process variability, and how they are manifested as errors in the design. We present classical approaches to hide such variability, including various forms of guard banding, overdesign, and redundancy. We then describe a number of strategies at successively higher levels of abstraction - covering the circuit, microarchitecture, compiler, operating systems and software applications - to monitor, detect, adapt to, and exploit the exposed variability. Finally we describe new approaches that attempt to eliminate guard banding at the software and architectural levels, and which opportunistically adjust to variability, and proactively conform to a deliberately underdesigned hardware with relaxed design and manufacturing constraints.
チュートリアル-4: 1月22日(火), 9:30 - 11:30, 13:00 - 15:00@Room 413
不揮発性メモリに基づく設計
- オーガナイザ:
- Prof. Sungjoo Yoo (Pohang University of Science and Technology, Korea)
- 講師:
- Prof. Sungjoo Yoo (Pohang University of Science and Technology, Korea)
- Prof. Dongkun Shin (Sungkyunkwan University, Korea)
概要:
Non-volatile memory is becoming more and more important in main memory and storage. This tutorial covers three non-volatile memory technologies, Flash memory, phase-change RAM (PRAM) and spin-torque transfer RAM (STT-RAM) which are already widely used (in the Flash memory case) or expected to play a crucial role in the near future.Flash memory is currently an indispensable storage component of mobile devices such as mobile phones and mobile tablet. In addition, Flash memory-based SSDs (Solid State Disks) are replacing traditional hard disk drives. To handle several special features of flash memory, FTL (Flash translation Layer) firmware performs address translation, garbage collection, wear-leveling, etc. This tutorial will introduce the special features of Flash memory, several technical issues on FTL and Flash file systems, and the multi-channel/way SSD architectures.
Phase change RAM (PRAM) is considered to be a practical candidate of large main memory (due to lower cost than DRAM and non-volatility) and fast storage (due to fast read and bit update capability with respect to the Flash memory). Basic operations of PRAM are explained including set/reset in single-level cells and ISPP in multi-level cells. Recent works on write endurance (e.g., error correction and wear levleing) and reliability (to address the R drift problem) are presented in details. Finally, the hybrid DRAM/PRAM organization is given to address the above problems as well as performance one (due to long read and write latency). We expect spin-torque transfer RAM (STT-RAM) can be utilized as on-chip cache and main memory especially when DRAM faces its scaling limit. The operation principles of STT-RAM, spin polarization, GMR, in-phase/perpendicular types, etc. are first explained. Then, recent studies on architectural solutions are presented especially to address the problems of write operation, e.g., long latency, high power consumption, backhopping, etc.
チュートリアル-5: 1月22日(火), 13:00 - 15:00, 15:30 - 17:30@Room 411+412
RF CMOS＆MEMS回路設計入門
- オーガナイザ:
- Prof. Kazuya Masu (Tokyo Institute of Technology, Japan)
- 講師:
- Prof. Noboru Ishihara (Tokyo Institute of Technology, Japan)
- Prof. Hiroshi Toshiyoshi (The University of Tokyo, Japan)
概要:
RF-CMOS/MEMS (radio frequency - complementary metal oxide semiconductor and micro electro mechanical systems) technology is thought to be an enabling power to deliver a more-than-Moore type added value to the VLSI for the next generation, and miniaturized micro RF systems integrated with CMOS VLSI and MEMS have been investigating aggressively.In this tutorial, the current status of RF COMS circuit and MEMS device design is introduced. In the analog RF CMOS circuit, transistor level topology is designed with various CAD tools; circuit simulators, magnetic-field analysis, chip layout editor, layout verification tools (DRC, LVS and LPE) and so on. It is reviewed how present RF engineers are designing the CMOS circuits with those tools. And the trend from the classical continuous voltage and continuous time domain design to discrete voltage and discrete time domain is also introduced and predict the future of RF CMOS design.
Moreover, as it is thought that small integration of the antenna and the interface circuit is indispensable to achieve miniaturized micro RF communication systems, the construction of the integrated design environment with the MEMS of the different kind devices becomes more important.
Multi-physics simulation is becoming an indispensable technique for MEMS to comprehend the system level behavior including electronics, mechanics, and/or other physics domain such as optics. We have newly developed a single platform simulation technique for MEMS by using a compact model solver for the mechanical equation-of-motion implemented as an analog computation circuit on an electrical circuit simulator such as Qucs, LTspice and Cadence Virtuoso with Verilog-a. In this tutorial, we review the conventional methods to develop an equivalent circuit model for MEMS and give a guidance to create a compact model for electrostatic micro actuators and sensors by translating the algebraic analytical model into an equivalent circuit model based on the non-linear independent current or voltage source.