University LSI Design Contest

The University LSI Design Contest has been conceived as a unique program at ASP-DAC. The purpose of the contest is to encourage research in LSI design at universities and its realization on a chip by providing opportunities to present and discuss the innovative and state-of-the-art design. The scope of the contest covers circuit techniques for (1) Analog / RF / Mixed-Signal Circuits, (2) Digital Signal Processer, (3) Microprocessors, (4) Custom Application Specific Circuits / Memories, and methodologies for (a) Full-Custom / Cell-Based LSIs, (b) Gate Arrays, (c) Field Programmable Devices.

This year, the University LSI Design Contest Committee received 36 designs from five countries/areas, and selected 21 designs out of them. The selected designs will be disclosed in Session 1D at four-minute presentations, followed by interactive discussions in front of their posters with light meals. To outstanding two designs, The Best Design Award and The Special Feature Award will be presented in the opening session. We sincerely acknowledge the other contributions to the contest, too. It is our earnest belief to promote and enhance research and education in LSI design in academic organizations. Please come to the University LSI Design Contest and enjoy the stimulating discussions.

  • Date: Wednesday, January 23, 2013
  • Place: Pacifico Yokohama, Conference Center, 4F
    • Oral Presentation : Room 416+417 (10:20-12:05)
    • Poster Presentation : Room 418 [Food will be served] (12:20-13:40)
  • Co-chairs: Tetsuo Hironaka (Hiroshima City University), Hiroshi Kawaguchi (Kobe University, Japan)
  • University LSI design contest committee
Time Title
1D-1 10:20 - 10:25 A 40 nm 144 mW VLSI Processor for Real-Time 60 kWord Continuous Speech Recognition
1D-2 10:25 - 10:30 A 24.5-53.6pJ/pixel 4320p 60fps H.264/AVC Intra-Frame Video Encoder Chip in 65nm CMOS
1D-3 10:30 - 10:35 A Low Power Multimedia Processor Implementing Dynamic Voltage and Frequency Scaling Technique
1D-4 10:35 - 10:40 A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Power Disturb Mitigation Technique
1D-5 10:40 - 10:45 A Physical Unclonable Function Chip Exploiting Load Transistors Variation in SRAM Bitcells
1D-6 10:45 - 10:50 Over 10-Times High-Speed, Energy Efficient 3D TSV-Integrated Hybrid ReRAM/MLC NAND SSD by Intelligent Data Fragmentation Suppression
1D-7 10:50 - 10:55 Highly Reliable Solid-State Drives (SSDs) with Error-Prediction LDPC (EP-LDPC) Architecture and Error-Recovery Scheme
1D-8 10:55 - 11:00 A 3Gb/s 2.08mm2 100b Error-Correcting BCH Decoder in 0.13um CMOS Process
1D-9 11:00 - 11:05 A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC Decoder in 65nm CMOS
1D-10 11:05 - 11:10 A 7.5Gb/s Referenceless Transceiver for UHDTV with Adaptive Equalization and Bandwidth Scanning Technique in 0.13um CMOS Process
1D-11 11:10 - 11:15 A 12.5 Gb/s/Link Non-Contact Multi-Drop Bus System with Impedance-Matched Transmission Line Couplers and Dicode Partial-Reponse Channel Transceivers
1D-12 11:15 - 11:20 315MHz OOK Transceiver with 38-uW Receiver and 36-uW Transmitter in 40-nm CMOS
1D-13 11:20 - 11:25 A Full 4-Channel 60GHz Direct-Conversion Transceiver
1D-14 11:25 - 11:30 A Sub-Harmonic Injection-Locked Frequency Synthesizer with Frequency Calibration Scheme for Use in 60GHz TDD Transceivers
1D-15 11:30 - 11:35 A Fractional-N Harmonic Injection-Locked Frequency Synthesizer with 10MHz-6.6GHz Quadrature Outputs for Software-Defined Radios
1D-16 11:35 - 11:40 A Ring-VCO-Based Sub-Sampling PLL CMOS Circuit with 0.73 ps Jitter and 20.4 mW Power Consumption
1D-17 11:40 - 11:45 Design of a Clock Jitter Reduction Circuit Using Gated Phase Blending Between Self-Delayed Clock Edges
1D-18 11:45 - 11:50 A 25-Gb/s LD Driver with Area-Effective Inductor in a 0.18-um CMOS
1D-19 11:50 - 11:55 A Regulated Charge Pump with Low-Power Integrated Optimum Power Point Tracking Algorithm for Indoor Solar Energy Harvesting
1D-20 11:55 - 12:00 A Low Voltage Buck DC-DC Converter Using On-Chip Gate Boost Technique in 40nm CMOS
1D-21 12:00 - 12:05 A 0.35-0.8V 8b 0.5-35MS/s 2bit/step Extremely-Low Power SAR ADC
Last Updated on: October 19, 2012