| Title | A Dual-Loop Injection-Locked PLL with All-Digital Background Calibration System for On-Chip Clock Generation |
| Author | *Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa (Tokyo Institute of Technology, Japan) |
| Page | pp. 21 - 22 |
| Keyword | PLL, All-digital, Calibration, Dual-loop, Clock Generation |
| Abstract | This paper presents a compact, low power, and low jitter dual-loop injection-locked PLL with synthesizable all-digital background calibration system for clock generation. Implemented in a 65nm CMOS process, this work demonstrates a 0.7-ps RMS jitter at 1.2 GHz while having 0.97-mW power consumption resulting in an FOM of -243dB. It also consumes an area of only 0.022mm2 resulting in the best performance-area trade-off system presented up-to-date. |
| Slides | |
| Title | A 950µW 5.5-GHz Low Voltage PLL with Digitally-Calibrated ILFD and Linearized Varactor |
| Author | *Sho Ikeda, Tatsuya Kamimura, Sangyeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu (Tokyo Institute of Technology, Japan) |
| Page | pp. 23 - 24 |
| Keyword | PLL, low voltage, low power |
| Abstract | This paper proposes an ultra-low-power 5.5-GHz PLL which employs a divide-by-4 injection-locked frequency divider (ILFD), which is calibrated by digital circuits, and linearity-compensated varactors for low supply-voltage operation. The proposed PLL was fabricated in 65nm CMOS. It shows a 1-MHz-offset phase noise of -106 dBc/Hz and the total power consumption of 950 µW at 5.5 GHz. |
| Slides | |
| Title | A Swing-Enhanced Current-Reuse Class-C VCO with Dynamic Bias Control Circuits |
| Author | *Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa (Tokyo Institute of Technology, Japan) |
| Page | pp. 25 - 26 |
| Keyword | Class-C, Current-Reuse, VCO, Phase noise, FoM |
| Abstract | A swing-enhanced current-reuse class-C VCO which can theoretically achieve same phase noise figure-of-merit (FoM) as other class-C VCOs at the lowest power consumption is presented. A swing enhancement in class-C operation and an oscillation robustness are achieved through dynamic bias control circuits for both NMOS and PMOS transistors. The proposed VCO has been fabricated in 180nm CMOS process while oscillating at 4.6 GHz. The measured phase noise is -119 dBc/Hz at 1 MHz offset while consuming 1.6 mA from 1.5 V supply. An FoM of -189 dBc/Hz is achieved. |
| Title | Design of A High-Performance Millimeter-Wave Amplifier Using Specific Modeling |
| Author | *Xiaojun Bi (National University of Singapore/Institute of Microelectronics, Agency for Science, Technology and Research, Singapore), Yongxin Guo (National University of Singapore, Singapore/National University of Singapore (Suzhou) Research Institute, China), M. Annamalai Arasu (Institute of Microelectronics, Agency for Science, Technology and Research, Singapore), M. S. Zhnag (National University of Singapore, Singapore), Yong Zhong Xiong, Minkyu Je (Institute of Microelectronics, Agency for Science, Technology and Research, Singapore) |
| Page | pp. 27 - 28 |
| Keyword | Amplifier, Modeling, SiGe |
| Abstract | In this design contest, the design methodology leading to a high performance Millimeter-wave amplifier in 0.13 µm SiGe BiCMOS is elaborated. Equivalent circuit models of the utilized cascode shielding structure are developed to assist the amplifier design. Meanwhile, final layouts of the passive connections are verified by 3D electromagnetic simulation in ANSYS HFSS. The implemented amplifier obtained a gain more than 45 dB in band, which is the gain record of silicon-based amplifiers in W-band. |
| Title | A Multi-Mode Reconfigurable Analog Baseband with I/Q Calibration for GNSS Receivers |
| Author | *Zheng Song, Nan Qi, Baoyong Chi, Zhihua Wang (Tsinghua University, China) |
| Page | pp. 29 - 30 |
| Keyword | Analog baseband, I/Q calibration, Reconfigurable, AGC |
| Abstract | A multi-mode reconfigurable analog baseband for GNSS receivers is presented. It provides I/Q mismatch auto-calibration with the aid of a FPGA. The 3rd/5th-order reconfigurable C-BPF supports various bandwidths from 2.2 to 10MHz and with center frequency from 3.996 to 16MHz. The AGC loop features 5-50dB gain range and 1dB step, and digital AGC control algorithms. The auto DC-offset cancellation is also integrated on-chip. The analog baseband consumes 6.5-13mA current. The measured image-rejection ratio is 45-55dB, improved by 22dB after calibration. |
| Slides | |
| Title | An 8b Extremely Area Efficient Threshold Configuring SAR ADC with Source Voltage Shifting Technique |
| Author | *Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro (Keio University, Japan) |
| Page | pp. 31 - 32 |
| Keyword | Threshold configuring, SAR ADC, Low power, Extremely small area |
| Abstract | An extremely low power and area efficient threshold configuring ADC (TC-ADC) for time interleaved ADC is proposed. The threshold configuring comparator (TCC) performs a binary search and 8b output is obtained by proposed source voltage shifting and threshold interpolation technique. Prototype ADC in 40nm CMOS occupies a core area of only 0.0038mm2. With a supply voltage of 0.7V, the ADC achieves 7.0 ENOB with 24MS/s. Peak FoM of 9.8fJ/conv. is obtained at 0.5V supply, which is over 15x improvement compared with conventional TC-ADC. |
| Slides | |
| Title | A Single-Inductor 8-Channel Output DC-DC Boost Converter with Time-Limited Power Distribution Control and Single Shared Hysteresis Comparator |
| Author | *Jungmoon Kim, Chulwoo Kim (Korea University, Republic of Korea) |
| Page | pp. 33 - 34 |
| Keyword | single-inductor multi-output (SIMO) DC-DC converter, cross-regulation, All-comparator control, comparator sharing technique, hysteresis comparator |
| Abstract | This paper describes a time-limited power distribution control (TPDC) technique that can be used for single-inductor multiple-output (SIMO) DC-DC converter with many unbalanced loads. Furthermore, the true all-comparator control technique that raises no stability or complexity issues is proposed. This all-comparator technique for SIMO converters is realized only with a single shared hysteresis comparator at a constant switching frequency of 800 kHz. The maximum efficiency reaches 92%. The fabricated chip with 8-channel outputs occupies 2.4×2.1 mm2 in a 0.35-μm CMOS process. |
| Title | A DC-DC Boost Converter with Variation Tolerant MPPT Technique and Efficient ZCS Circuit for Thermoelectric Energy Harvesting Applications |
| Author | *Jungmoon Kim, Minseob Shim, Junwon Jung, Heejun Kim, Chulwoo Kim (Korea University, Republic of Korea) |
| Page | pp. 35 - 36 |
| Keyword | Battery charger, boost converter, energy harvesting, maximum power point tracking, variation |
| Abstract | This paper presents a boost converter with the maximum power point tracking (MPPT) technique for thermoelectric energy harvesting (EH) applications. The technique realizes variation tolerance by adjusting the switching frequency fSW of the converter. A finely controlled zero-current switching (ZCS) scheme together with the accurate MPPT technique enhances the overall efficiency (η) of the converter because of an optimal turn-on time generated by a one-shot pulse generator that is proposed. Moreover, the ZCS technique can deal with low and high temperature differences applied to the thermoelectric generator. Experimentally, the converter implemented in a 0.35 μm BCDMOS process had a peak η of 72% at the input voltage VIN of 500mV while supplying a 5.62V output. |
| Title | 7.3 Gb/s Universal BCH Encoder and Decoder for SSD Controllers |
| Author | *Hoyoung Yoo, Youngjoo Lee, In-Cheol Park (Korea Advanced Institute of Science and Technology, Republic of Korea) |
| Page | pp. 37 - 38 |
| Keyword | BCH enc/dec, universal BCH encoder, multi-mode, syndrome calculation |
| Abstract | This paper presents a universal BCH encoder and decoder that can support multiple error-correction capabilities. A novel encoding architecture and on-demand syndrome calculation technique is proposed to reduce both hardware complexity and power consumption. Based on the proposed methods, 32-parallel universal encoder and decoder are designed for BCH (8192+14t, 8192, t) codes, where the error-correction capability t is configurable to 8, 11, 16, 24, 32, and 64. The prototype chip achieves a throughput of 7.3 Gb/s and occupies 2.24 mm2 in 0.13μm CMOS technology. |
| Title | A High-Speed and Low-Complexity Lens Distortion Correction Processor for Wide-Angle Cameras |
| Author | *Won-Tae Kim, Hui-Sung Jeong, Gwang-Ho Lee, Tae-Hwan Kim (School of Electronics, Telecommunication and Computer Engineering, Korea Aerospace University, Republic of Korea) |
| Page | pp. 39 - 40 |
| Keyword | barrel distortion, wide-angle camera, memory interface, raster scan, hardware implementation |
| Abstract | This paper presents a high-speed and low-complexity lens distortion correction processor for wide-angle cameras. In the proposed processor, the conventional correction process is modified to be performed incrementally so as to reduce the hardware complexity. In addition, an efficient memory interface is proposed by utilizing the locality of the memory access in the correction process. The proposed processor is implemented with 17.2K logic gates in a 0.11 µm CMOS process and its correction speed is 205 Mpixels/s. |
| Slides | |