| Title | Efficient Techniques for the Capacitance Extraction of Chip-Scale VLSI Interconnects Using Floating Random Walk Algorithm |
| Author | *Chao Zhang, Wenjian Yu (Tsinghua Univ., China) |
| Page | pp. 756 - 761 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | 3DLAT: TSV-Based 3D ICs Crosstalk Minimization Utilizing Less Adjacent Transition Code |
| Author | *Qiaosha Zou, Dimin Niu, Yan Cao (Pennsylvania State Univ., U.S.A.), Yuan Xie (AMD, China/Pennsylvania State Univ., U.S.A.) |
| Page | pp. 762 - 767 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | Tackling Close-to-Band Passivity Violations in Passive Macro-Modeling |
| Author | *Moning Zhang, Zuochang Ye (Tsinghua Univ., China) |
| Page | pp. 768 - 773 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | HIE-Block Latency Insertion Method for Fast Transient Simulation of Nonuniform Multiconductor Transmission Lines |
| Author | *Takahiro Takasaki, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ., Japan) |
| Page | pp. 774 - 779 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |