Designers' Forum

The Designers' Forum is a unique program that will share design experience and solutions of actual product designs of the industries. This year's program includes the invited talks on the next generation car electronics and 4K/8K TV technologies, and also includes panel discussions on data-centric computing platform and IP-based SoC design and IP design innovations.

  • Date: January 21-22, 2015
  • Place: Makuhari Messe, International Conference Hall, 1F, Room 103
  • Designers' Forum Chair: Yoshio Masubuchi (Toshiba Corp., Japan)
  • Designers' Forum Chair: Koji Inoue (Kyushu University, Japan)

Date/Time Title
5S January 21, 13:50-15:30, Room 103 Oral Session:
Car Electronics
6S January 21, 15:50-17:30, Room 103 Panel Discussion:
Challenges in the Era of Big-Data Computing
8S January 22, 13:50-15:30, Room 103 Oral Session:
Technology Trend toward 8K Era
9S January 22, 15:50-17:30, Room 103 Panel Discussion:
IP base SoC design and IP design innovation

Session 5S: Wednesday, January 21, 13:50-15:30, Room 103

Oral Session: Car Electronics

Organizer: Shinichi Shibahara (Renesas Electronics Corp., Japan)
Session chair: Koji Inoue (Kyushu Univ., Japan)

Three practical design examples of up-to-date automobile developments based on car electronics are described. For designing automobiles accurately and effectively, this session covers vertical integration from systems modeling to verify top level architecture of the automobile system to power devices for fundamental energy conversion. In details, the first presentation of this session describes systems modeling in automotive electrical and electronic (E/E) architecture. The second is the development of the SoC (System on chip) for ADAS (Advanced driving assistance system) applications based on an image recognition algorithm, and the final presentation forecast power devices trends and explains some design examples of the extremely reliable and efficient power devices transferring energy between the battery and the motor/generator.

  • 1: Systems Modeling for Additional Development in Automotive E/E Architecture

    Hidekazu Nishimura (Keio Univ., Japan)

    Systems modeling in automotive electrical and electronic (E/E) architecture is described according to systems engineering process. The purpose of my presentation is to show the importance of system architecture using SysML (Systems Modeling Language). Access and protection system is treated as an example designed in additional development based on the new requirements such as "user friendliness" and "omotenashi". It is shown that model-based systems engineering is effective and useful to obtain system architecture.

  • 2: Implementation and Evaluation of Image Recognition Algorithm for An Intelligent Vehicle using Heterogeneous Multi-Core SoC

    Nau Ozaki, Masato Uchiyama, Yasuki Tanabe, Shuichi Miyazaki, Takaaki Sawada, Takanori Tamai, and Moriyasu Banno (Toshiba Corp., Japan)

    Image recognition algorithm is becoming one of the most important technology for intelligent vehicle application such as Advanced Driver Assistance Systems (ADAS), however its computational costs are still considerably high. To realize such applications using image recognition algorithm as hard real-time task with low power consumption, we have developed heterogeneous multi-core SoC specialized for image recognition [1]. Subsequently, several image recognition applications have been developed using this SoC. In this paper, we address two ADAS applications and image recognition algorithms for them, and evaluate them on the SoC. The results of the evaluation show that the SoC allows these applications to run with significantly low power consumption comparing with general purpose CPU..

  • 3: Trend in Power Devices for Electric and Hybrid Electric Vehicles

    Khalid Hussein, Akira Fujita, and Katsumi Sato (Mitsubishi Electric Corp., Japan)

    Since the very successful release of the world's first mass-produced HEV (hybrid electric vehicle) in 1997, the number of HEVs as well as EVs (electric vehicles) has been gradually increasing in major cities around the world. Reliable and efficient power devices transferring energy between the battery and the motor/generator represent the heart of the electric power-train that realizes the electric-mobility concept. The objective of this presentation is to give a quick preview of the early mass-produced power modules for EV/HEVs and to highlight the advancement achieved so far in addressing the automotive severe reliability and high performance requirements. The presentation will also cover some of the power devices trends in terms of the major pillars comprising automotive power modules: (1) power chip technology, (2) packaging technology, and (3) functional integration.

Session 6S: Wednesday, January 21, 15:50-17:30, Room 103

Panel Discussion: Challenges in the Era of Big-Data Computing

Organizer: Koji Inoue (Kyushu Univ., Japan)

The advent of big data era may require a paradigm shift for designing computing systems. The amount of data to be obtained from real world increases exponentially every year, whereas the speed of performance improvements of conventional computing systems is quite slow compared to such rapid grows of big-data applications. So, now it is the time to revisit computer system architecture and its design. The panel discusses the direction of computing platforms in order to satisfy such performance requirements on next generation big-data era.

Moderator:Koichiro Yamashita (Research manager, Fujitsu Laboratories Ltd., Japan)
Panelists: Kento Aida (Professor, Information Systems Architecture Research Division, National Institute of Informatics, Japan)
Derek Chiou (Architect, Microsoft, USA / Associate Professor, Electrical and Computer Engineering, The University of Texas at Austin, USA)
Hiroshi Nakamura (Director, Information Technology Center, The University of Tokyo)
Hiroyuki Tanaka (Senior Research Engineer, Supervisor, NTT Network Innovation Laboratories, Nippon Telegraph and Telephone Corporation, Japan)
Iwao Yamazaki (Manager, Next Generation Technical Computing Unit LSI Development Div., Fujitsu LTD., Japan)

Session 8S: Thursday, January 22, 13:50-15:30, Room 103

Oral Session: Technology Trend toward 8K Era

Organizer: Hiroe Iwasaki (NTT Media Intelligence Laboratories, Japan)
Session Chair: Masaitsu Nakajima (System LSI Business Division Panasonic Corporation, Japan)

From 2014, 4K/UHD CS digital test broadcasting has been already started, and 4K VOD services will be started in 2015 by adopting the latest CODEC standard, H.265/HEVC. Not only 4K, 8K terrestrial test digital broadcasting and 8K terrestrial practical digital broadcasting are planed to be started in 2016 and 2018 respectively. In this session, technology trend toward 8K era will be discussed from various perspective. Four very interesting talks from the key persons of NexTV forum, 8K panel provider, SoC provider and CODEC researcher will be presented.

  • 1: The Prospects of Next Generation Television - Japan's Initiative to 2020 -

    Keiya Motohashi (NetTV Forum, Japan)

    In japan, Telecommunications Authority supposed the first grand schedule for launching and spread of UHDTV & advanced smart TV, called 'roadmap', in June 2013. The roadmap suggested that business-based 4KTV & 8KTV broadcast would be launched until 2020. In 2014, experimental 4K broadcast started and 'roadmap' was revised. Comprehensively, grand schedule for launching UHDTV in Japan is said to move up about 2 years.

  • 2: 8K LCD : Technologies and challenges toward the realization of SUPER Hi-VISION TV

    Takeshi Kumakura (SHARP Corporation, Japan)

    Since 2011, we have successfully developed a number of 8K LCD prototypes for SUPER Hi-VISION. The latest prototype has an 85-inches panel of 7680 by 4320 pixels and the frame rate has been achieved 120Hz and the color system has been expanded to a wide-gamut which is compliant with BT2020. Furthermore, the input interface has been upgraded to a novel optical fiber system which is capable to transmit 256Gbps with one cable.

  • 3: The world's 1st Complete-4K SoC Solution with Hybrid Memory System

    Daisuke Murakami, Yuki Soga, Daisuke Imoto, Yoshiharu Watanabe, Takashi Yamada (Panasonic Corporation, Japan)

    The 4K2K Display market is expanding faster than expected. For this market, we introduce the world's 1st Complete-4K SoC solution with hybrid memory system. This SoC supports High Efficiency Video Coding (HEVC) 10bit 4K 60p decode, graphics processing, picture blending, and external video input/output. These operations can be performed simultaneously with 4K quality. To realize that capability, we adopt highly efficient novel hybrid memory system with Wide-IO 266 memory and DDR3-1866 memory (24.4GB/s, 20Gbits).

  • 4: H.265/HEVC Encoder for UHDTV

    Mitsuo Ikeda (NTT, Japan)

    In recent years, the growing demand for ultra-high-definition television (UHDTV) services has generated the rapid development of UHDTV technologies. A key issue in providing UHDTV services is achieving efficient video coding. This paper presents an outline of H.265/HEVC, the latest video coding standard, and reviews the technologies it includes.

Session 9S: Thursday, January 22, 15:50-17:30, Room 103

Panel Discussion: IP base SoC design and IP design innovation

Organizer: Nobuyuki Nishiguchi (Cadence Design Systems, Japan)

Recent SoC uses a lot of IP's. This session discuss what innovation will happen in the next generation of SoC design with IP's and IP design itself. Four major IP vendors are invited and will talk their views for future design innovation of SoC with their IP's which include numbers and types of IP's such as digital, analog, RF and even a MEMS, variety such as CPU, GPU, memory, bus, interface and so on, usage models in design hierarchy and its modeling and integration methods of those IP's. And also in order to achieve the SoC design innovation they will mention IP itself design methodology including planning, specification, implementation, verification, validation and qualification. Comments, questions and discussions with audiences at the panel are welcome.

Moderator:Toshihiro Hattori (General Manager, Development Division 1, Renesas System Design Co., Ltd., Japan)
Panelists: Hironori Ando (Chief Japan IP R&D Center, Solutions Group, Synopsys, Japan)
Kevin Yee (Marketing Director, IP Group, Cadence, USA)
Randy Smith (Vice President, Marketing, Sonics, USA)
Neil Parris (Senior Product Manager System & Software, ARM, UK)

Last Updated on: October 30, 2014