Tutorials

ASP-DAC 2015 offers attendees a set of two-hour intense introductions to specific topics. Each tutorial will be presented twice a day to allow attendees to cover multiple topics. If you register for tutorials, you have the option to select three out of the six topics.

  • Date: Monday, January 19, 2015 (9:30 - 17:30)
  • Place: Makuhari Messe, International Conference Hall, 1F
Room 102 Room 103 Room 104 Room 105
9:30 - 11:30 Tutorial-1
Ultra-low power ultra-low voltage design techniques in Fully Depleted SOI technologies
Tutorial-2
Leading-Edge Lithography and TCAD
Tutorial-3
Normally-Off Computing: Synergy of New Non-Volatile Memories and Aggressive Power Management
Tutorial-4
Hardware Trust in VLSI Design and Implementations
13:00 - 15:00 Tutorial-1
Ultra-low power ultra-low voltage design techniques in Fully Depleted SOI technologies
Tutorial-2
Leading-Edge Lithography and TCAD
Tutorial-5
High-Level Synthesis for FPGAs: From Software to Programmable Hardware
Tutorial-6
Electronic Design Automation for Nanotechnologies
15:30 - 17:30 Tutorial-3
Normally-Off Computing: Synergy of New Non-Volatile Memories and Aggressive Power Management
Tutorial-4
Hardware Trust in VLSI Design and Implementations
Tutorial-5
High-Level Synthesis for FPGAs: From Software to Programmable Hardware
Tutorial-6
Electronic Design Automation for Nanotechnologies



(Student Grp: a group of four or more students from the same affiliation)
Advance (JPY) Late (JPY)
Member 22,000 26,000
Non-Member 26,000 30,000
Student 14,000 16,000
Student Grp 10,000 12,000



Tutorial-1: Monday, January 19, 9:30 - 11:30, 13:00 - 15:00@Room 102

Ultra-low power ultra-low voltage design techniques in Fully Depleted SOI technologies

Organizer:
Andreia Cathelin (STMicroelectronics)
Speakers:
Giorgio Cesana (STMicroelectronics)
Edith Beigné (CEA-Leti)
Nobuyuki Sugii (LEAP)

Tutorial Outline:

Electronics is more and more pervasive in everyday life: smartphones, connected cars, wearable, Internet of Things... After decades of steady gradual evolution, the semiconductor industry is now facing its biggest and most interesting challenge: while in the last few years the number of mobile devices has significantly grown year after year, the revolution of the Internet of Things promises an exponential growth of connected devices. Semiconductor technology is the key enabler of today applications, making possible the impossible by allowing device miniaturization and co-integration. Traditional planar CMOS technology is mature and low cost, but limited in power consumption efficiency and performances from the 28nm node. These 3 talks tutorial event will bring a highlight in planar thin film fully depleted CMOS technologies that enhance innovative solutions for very energy efficient systems.

The first talk will focus on the UTBB FDSOI technology from STMicroelectronics, presenting the latest technology highlights and mapped on the system design needs for energy efficient logic and also analog/RF designs. The second talk, by CEA-Leti, will get in-deep of complex digital circuit design, focusing on a 32-bit VLIW DSP exhibiting outstanding silicon results in terms of speed and energy. All the design techniques enhancing exceptional energy efficient operation will be carefully detailed.

And finally, the third talk from LEAP will also present ultra-low power system design in the SOTB FDSOI technology. Design techniques will be highlighted in the frame of an energy efficient micro-controller design.

Theme 1: Planar UTBB FD-SOI technology for highly energy efficient devices
Speaker: Giorgio Cesana (STMicroelectronics)

The revolution of the Internet of Things promises an exponential growth of connected devices. To sustain this market demand, the semiconductor industry requires a real breakthrough in energy efficiency both for the connected devices and for the communication infrastructure. Innovative solutions for very energy efficient systems are mandatory to continue the growth the semiconductor industry enjoyed, covering ultra-low power systems, energy management and harvesting. We will present the development of the 28nm UTBB FD-SOI (Ultra-Thin Body and Buried-oxide Fully Depleted Silicon On Insulator) technology and its main characteristics, especially suited for highly energy efficient operation (even in ultra-low voltage conditions), not limited to digital logic but also on memory bit-cells and exceptional analog/RF characteristics. Several application domains will be illustrated demonstrating how the technology can enable new and innovative applications in the field of IoT, wearable, mobile and server.

Theme 2: FDSOI circuit design for a better energy efficiency: Wide operating range and ULP applications
Speaker: Edith Beigné (CEA-Leti)

With the increasing complexity of today's MPSoC applications, extremely high performance has become the main requirement. Using energy efficient architectures is the only way to achieve a good compromise between speed and power. For each functional point, the architecture should be able to find an optimum energetic state while considering applicative constraints. The emerging solution is to use Adaptive Voltage and Frequency Scaling (AVFS) architectures, able to dynamically adapt its optimum functional point to the real Process-Voltage-Temperature (PVT) case. The objective is to save power at same speed or to increase the speed for an equivalent power budget. Moreover, the need to increase the speed at low voltage while maintaining very high speed at nominal voltage is still a key issue for the convergence between very high speed and ultra low power. Designing Ultra Wide Voltage Range (UWVR) systems at the nanometer regime introduces many challenges due to the emphasis of parasitic phenomenon effects driven by the scaling of bulk MOSFETs, making circuits more sensitive to the manufacturing process fluctuations and less energy efficient. Undopped thin-film planar FDSOI devices are being investigated in this presentation as an alternative to bulk devices in 28nm node and beyond, thanks to its excellent short-channel electrostatic control, low leakage currents and immunity to random dopant fluctuation. This presentation will highlight the development of an UWVR multi-VT design platform in FDSOI planar technology on Ultra Thin Body and Box (UTBB) for the 28nm node. The efficient use of an adaptive voltage and frequency scaling architecture has been proved on a 32-bit VLIW DSP exhibiting outstanding silicon results in terms of speed and energy. The use of an efficient Body Biasing (BB) shows an extremely efficient performance tuning for high energy efficiency. We will also explore FDSOI benefits for new ULP applications and IoT perspectives.

Theme 3: Ultra low-power system design based on SOTB FDSOI Technology
Speaker: Nobuyuki Sugii, LEAP

Ultralow-voltage (ULV) operation of CMOS circuits is effective for significantly reducing the power consumption of the circuits. Although the operation at the minimum energy point (MEP) is effective, its slow operating speed has been an issue. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for the ultralow-power (ULP) electronics because of its small variability and back-bias control. These advantages of SOTB enable a power and performance optimization with adaptive Vth control at ULV and can achieve the ULP operation with acceptably high speed and low leakage. This talk summarizes these issues and reviews recent results on the ULV SOTB circuits including a microcontroller chip.


Tutorial-2: Monday, January 19, 9:30 - 11:30, 13:00 - 15:00@Room 103

Leading-Edge Lithography and TCAD

Organizer:
Shigeki Nojima (Toshiba)
Speakers:
Seiji Nagahara (Tokyo Electron)
Tomoyuki Matsuyama (Nikon)
Shigyo Naoyuki (Toshiba)

Tutorial Outline:

As feature size becomes below the resolution limit of lithography, several complementary techniques of lithography and process have emerged, such as multiple patterning technology and block co-polymer directed self-assembly (DSA). Since these techniques start with ArF immersion lithography, the exposure system is still one of the keys for the fine patterning. For example, overlay error of an exposure system directly causes CD variation on the multiple patterning and pattern shift from the ideal position on DSA. In addition, the shrink of the feature size causes serious statistical process fluctuation, which has influence on device and circuit performance. As virtual manufacturing, TCAD is one of useful tools for robust designs of process, device and circuit.

This tutorial will provide the overview of cutting-edge technologies for ArF immersion exposure system, DSA and TCAD. The topics will cover recent development status, challenges and possible future directions. Furthermore, a design considering manufacturability becomes much important when the new technologies are applied. In this tutorial, design for manufacturability, such as DSA friendly design, will also be discussed.


Tutorial-3: Monday, January 19, 9:30 - 11:30@Room 104, 15:30 - 17:30@Room 102

Normally-Off Computing: Synergy of New Non-Volatile Memories and Aggressive Power Management

Organizers:
Hiroshi Nakamura (The University of Tokyo)
Takashi Nakada (The University of Tokyo)
Speakers:
Takashi Nakada (The University of Tokyo)
Shinobu Fujita (Toshiba Corporate R&D Center)

Tutorial Outline:

Normally-off computing is a way of computing where inactive components of computer systems are aggressively powered off with the help of new non-volatile memories (NVMs). Simple power gating cannot fully take the chances of power reduction since volatile memories lose data when power supply is off. With new NVMs, they can maintain their content without power supply. Thereore, a synergetic effect for power gating is highly expected. Hence, this tutorial presents basic design methodologies for normally-off computing, discusses major challenges and approaches in it and introduces key features related to power gating and new generation NVMs. Regarding power gating, granularity of power domain and performance/energy overheads are major concerns. For non-volatile memory, access time and read/write energy are important problems. Essentially, it is important to understand what kind of characteristics affect the performance and energy consumption. There are trade-offs, such as break even time (BET), not only within each technology but also cross-technologies. For example, when the scheduling of a task is changed, the optimal power management may also be different. Thus, to realize normally-off computing, hardware/software co-design and co-optimization are required. This is key for not only system designers, but also hardware engineers and software developers.


Tutorial-4: Monday, January 19, 9:30 - 11:30@Room 105, 15:30 - 17:30@Room 103

Hardware Trust in VLSI Design and Implementations

Organizers:
Kazuo Sakiyama (The University of Electro-Communications)
Makoto Nagata (Kobe University)
Speakers:
Patrick Schaumont (Virginia Tech, US)
Swarup Bhunia (Case Western Reserve University, US)
Kazuo Sakiyama (The University of Electro-Communications, JP)
Makoto Nagata (Kobe University, JP)

Tutorial Outline:

This tutorial provides introductory perspectives of hardware trust in the design and implementation of VLSI systems for security applications. The talks by four experts cover the front-end understandings of threats and countermeasures to the back-end knowledge including counterfeiting, active and passive attacks through side channels of IC chips.

Talk-1: Threats and Countermeasures from Protocols to Secure Hardware Implementation
Patrick Schaumont (Virginia Tech, US)

The first talk will make compare and contrast Secure Hardware Design with conventional hardware design, by means of an overview of the threats and countermeasures at various abstraction levels in a hardware design flow. It explains the typical capabilities of an adversary, the nature of the attacks, and the resulting risk to secure hardware to fail a given security policy. The need for design methods will be emphasized to address threats to Secure Hardware, systematically and efficiently.

Talk-2: IC Counterfeiting: Challenges and Solutions (PUFs, Aging Sensors, and Integrity Analysis)
Swarup Bhunia (Case Western Reserve University, US)

The second talk will focus on the growing threat of IC counterfeiting covering the attack modes and major solution paradigms including physical unclonable functions (PUFs) and aging sensors. It will explain different types of counterfeit ICs by providing examples and attack scenarios. Next, it will describe several major classes of countermeasures based on common security primitives such as PUFs and aging sensors, as well as through IC integrity analysis. Implementation of various types of PUFs and aging sensors, their operating principles and relative merits/demerits will be discussed. The metrics will be emphasized to evaluate the security primitives. Finally, the talk gives efficient IC integrity analysis approaches that can characterize an IC to isolate anomalous behavior leading to detection of counterfeit instances.

Talk-3: Fault Analysis for Cryptosystems: Introduction to Differential Fault Analysis and Fault Sensitivity Analysis
Kazuo Sakiyama (The University of Electro-Communications, JP)
The third talk will introduce several techniques for fault analysis including Differential Fault Analysis (DFA) and Fault Sensitivity Analysis (FSA). Through the previous researches of DFA on AES (Advanced Encryption Standard), several key-recovery attacks and their optimality are discussed in a quantitative way. As the second topic, we look into the details of FSA that was proposed in 2010, and compare the feature with DFA. The talk gives possible countermeasures and discusses future collaboration between hardware designers and cryptographers.

Talk-4: Side Channel Leakage in Cryptographic Modules: Introduction to Physical Origins and Attack Models
Makoto Nagata (Kobe University, JP)
The fourth talk will cover understandings of side-channel information leakage in cryptographic modules physically implemented on an IC chip. Side-channel attack (SCA) models on passive leakages by power current consumption will be focused, and demonstrated on power current flows in an actual Si chip in assembly. Some ideas of countermeasures to the information leakage at circuit level will also be examined.


Tutorial-5: Monday, January 19, 13:00 - 15:00, 15:30 - 17:30@Room 104

High-Level Synthesis for FPGAs: From Software to Programmable Hardware

Organizer:
Jason Anderson (University of Toronto)
Speakers:
Jason Anderson (University of Toronto)
Ben Carrion Schafer (Hong Kong Polytechnic University)

Tutorial Outline:

High-level synthesis (HLS) was first proposed in the 1980s, and after spending decades in the shadows of mainstream digital design, there has been tremendous "buzz" around HLS technology in recent years. Indeed, HLS has been gaining traction as a design methodology for field-programmable gate arrays (FPGAs) to improve designer productivity and ultimately, to make FPGA technology accessible to software engineers possessing limited hardware expertise. The hope is that down the road, software developers could use HLS to realize FPGA-based accelerators customized to applications that work in tandem with standard processors to raise computational throughput and energy efficiency. Both of the main FPGA vendors have been investing heavily in HLS in recent years and in this tutorial, we provide a crash course on FPGA HLS, from both the academic research and industrial perspectives. We review the core steps taken by modern HLS tools and the underlying algorithms used inside. We then consider how the style of the high-level language code input to HLS influences the circuit produced and its performance. Special attention will be given to the differences in HLS for FPGAs, custom ASICs, and other IC media, such as coarse-grained arrays. We discuss the typical "knobs" available to an HLS user to enable design-space exploration, for example, to control loop pipelining, resource sharing, and other optimizations. We conclude by discussing current HLS research and mention some of the remaining challenges for HLS that possibly hinder its broader update in the digital design community.

The tutorial will be of interest to be EDA researchers, as well as current and future users of FPGA HLS.


Tutorial-6: Monday, January 19, 13:00 - 15:00, 15:30 - 17:30@Room 105

Electronic Design Automation for Nanotechnologies

Organizers:
Pierre-Emmanuel Gaillardon (EPFL)
Giovanni De Micheli (EPFL)
Speakers:
Pierre-Emmanuel Gaillardon (EPFL)
Luca Amaru (EPFL)
Anupam Chattopadhay (Nanyang Technical University)
Subhasish Mitra (Stanford University)

Tutorial Outline:

Nanoscale emerging technologies hold the promises of drastic improvements of the key design metrics, i.e., area, delay and power consumption, of near-future computing systems. In addition to a pure improvement of the device parameters, many novel technologies exploit unconventional physical phenomena leading to larger computation capabilities at the device level. Such fundamental paradigm change precludes standard CMOS design techniques to fully leverage the performances of advanced devices. In addition to unlocking the logic capabilities of the devices from a logic synthesis perspective, the design methodologies should also consider carefully the manufacturing of the technology, i.e., the physical design, to maximize the fabrication yield.

In this tutorial, we will introduce the importance for tight links between design methodologies and technology to fully exploit emerging devices. The tutorial will cover 3 principal themes: logic optimization and underlying data structures, technology mapping and physical design. To get a direct sense on the importance of design automation for nanotechnologies, each theme will be associated and discussed through a specific technology: controllable-polarity nanowire transistors, quantum gates and carbon nanotubes transistors respectively.

Theme 1: Logic Optimization - Majority and Biconditional Logic:
Dr. Pierre-Emmanuel Gaillardon, Mr. Luca Amaru, EPFL, Lausanne, Switzerland

Many logic representation forms, and related synthesis algorithms, are based on primitive conjunction, disjunction, if-then-else and complementation logic operators. Such set of primitives was introduced because of its great implementation with standard CMOS technologies. However, nanotechnologies typically support natively different set of operators and primitives. In this first part, we discuss a generalization of such primitives, using majority, biconditional and complementation logic operators.
Leveraging an enhanced expressive power, we extend the capabilities of modern logic synthesis tools in fully unlocking the performances offered by nanotechnologies. First, we focus on majority logic and present Majority-Inverter Graphs (MIGs), along with their native Boolean algebra, for efficient logic optimization and synthesis. As compared to traditional AND/OR-INV graphs, MIGs show stronger properties and better synthesis results. Second, we focus on biconditional logic. We present Biconditional Binary Decision Diagrams (BBDDs), a new canonical decision diagram driven by a biconditional expansion. BBDDs are often more compact than traditional decision diagrams, especially for arithmetic circuits. We show the beneficial effect of BBDD rewriting of arithmetic circuits prior to logic synthesis in the context of nanotechnologies.

Theme 2: Technology Mapping - Reversible Logic Synthesis:
Pr. Anupam Chattopadhay, Nanyang Technical University, Singapore

To enable computing devices go beyond the Von Neumann-Landauer (VNL) limit of energy dissipation per bit, reversible logic circuits were initially studied. Recently, the field is receiving a renewed interest, since multiple emerging technologies, e.g., nano- and photonic circuits having devices without gain and Quantum computing on classical Boolean logic, are fundamentally relying on reversible circuit implementations. While the final technology mapping for these devices are dependent on the device library, an important step is to realize a given function in terms of device-independent reversible logic structures and perform necessary optimizations therein. This is driven by the researchers in the area of reversible logic synthesis. In this second part of the tutorial, we will review major directions in reversible logic synthesis with a particular emphasis on the logic representation.

Theme 3: Physical Design - Robust System Design at the Nanoscale:
Pr. Subhasish Mitra, Stanford University, USA

Emerging technologies are inherently highly subject to imperfections and variations that pose major obstacles to the design of robust and very-large-scale digital systems. This is particularly impacting bottom-up technologies such as carbon nanotubes. Despite these strong limitations, major achievements have been obtained recently in building reliable systems out of this imperfect technology, e.g., the Stanford Carbon Nanotube Computer. Imperfection-immune design techniques and CAD tools able to cope with the high variability of the technology enabled this major breakthrough. The last part of this tutorial will focus on reviewing the physical design techniques required to design reliable systems out of nanoscale devices.
Last Updated on: November 7, 2014