Sponsored By:
Designers' Forum
Designers' Forum is a new program that shares design experience and solutions of real product designs of the industries whose topics include the CELL and mobile designs, panels of top 10 design issues and system verification.
- Message from Designers' Forum Chairs
- Date: January 26-27, 2006
- Place: Pacifico Yokohama, Conference Center, Small Auditorium, 5F
- Industry Liaison Chair: Haruyuki Tago (TOSHIBA CORPORATION)
- Industry Liaison
- Designers' Forum Chair: Makoto Ikeda (University of Tokyo)
| Date/Time | Title | ||
| 5D | January 26 / 13.30 - 15.30 | Low Power Design | |
| 6D | January 26 / 16.30 - 18.00 | Functional Verification---now and future--- | |
| 8D | January 27 / 13.30 - 15.30 | Cell Processor | |
| 9D | January 27 / 16.30 - 18.00 | Top 10 Design Issues by LSI Designers versus EDA Developers |
5D : Thursday, January 26, 13:30-15:30, Small Auditorium, 5F
Invited Talks: Low Power Design
5D-1: Low-Power Design Methodology for Module-wise Dynamic Voltage and Frequency Scaling with Dynamic De-skewing Systems
Takeshi Kitahara, Hiroyuki Hara, Shinichiro Shiratake (Toshiba, Japan), Yoshiki Tsukiboshi (Toshiba Microelectronics Co., Japan), Tomoyuki Yoda, Tetsuaki Utsumi, Fumihiro Minami (Toshiba, Japan)
5D-2: Single-Chip Multi-Processor Integrating Quadruple 8-Way VLIW Processors with Interface Timing Analysis Considering Power Supply Noise
Satoshi Imai (Fujitsu Lab., Japan)
5D-3: A System-level Power-estimation Methodology based on IP-level Modeling, Power-level Adjustment, and Power Accumulation
Masafumi Onouchi, Tetsuya Yamada (Hitachi Ltd., Japan), Kimihiro Morikawa, Isamu Mochizuki, Hidetoshi Sekine (Renesas, Japan)
5D-4: PowerViP: SoC Power Estimation Framework at Transaction Level
Ikhwan Lee, Hyunsuk Kim, Peng Yang, Sungjoo Yoo, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo (Samsung Electronics, Republic of Korea)
6D: Thursday, January 26, 16:30-18:00, Small Auditorium, 5F
Panel Discussion: Functional Verification -now and future-
Organizer: Haruyuki Tago (TOSHIBA)
Moderator: Yoshio Masubuchi (TOSHIBA)
Panelists: Sanjay Gupta (IBM), Michael Stellfox (Cadence), Tetsuji Sumioka (Sony), Sunao Torii (NEC)
8D: Friday, January 27, 13:30-15:30, Small Auditorium, 5F
Invited Talks: `Cell' Processor
8D-1: A New Test and Characterization Scheme for 10+ GHz Low Jitter Wide Band PLL
Kazuhiko Miki (Toshiba, Japan), David Boerstler, Eskinder Hailu, Jieming Qi, Sarah Pettengill (IBM Microelectronics, United States), Yuichi Goto (Toshiba, Japan)
8D-2: An SPU Reference Model for Simulation, Random Test Generation and Verification
Yukio Watanabe (Toshiba, Japan)
8D-3: A Cycle Accurate Power Estimation Tool
Rajat Chaudhry, Daniel Stasiak, Stephen Posluszny, Sang Dhong (IBM, United States)
8D-4: Key Features of the Design Methodology Enabling a Multi-Core SoC Implementation of a First-Generation CELL Processor
D. Pham, E. Behnen, M. Bolliger, S. Gupta, H. P. Hofstee, P. Harvey, C. Johns, J. Kahle (IBM, United States), A. Kameyama (Toshiba America Electronic Components, United States), J. Keaty, B. Le, S. Lee (IBM, United States), Y. Masubuchi (Toshiba America Electronic Components, United States), T. Nguyen, J. Petrovick, M. Pham, S. Posluszny, M. Riley (IBM, United States), M. Suzuoki (Sony Computer Entertainment, Japan), J. Verock, J. Warnock, S. Weitzel, D. Wendel (IBM, United States)
9D: Friday, January 27, 16:30-18:00, Small Auditorium, 5F
Panel Disussion: Top 10 Design Issues by LSI Designers versus EDA Developers
Organizer: Haruyuki Tago (TOSHIBA)
Moderator: Yoshiaki Hagihara (Sony)
Panelists: Raul Camposano (Synopsys), Soo-Kwan Eo (SAMSUNG), Joe Sawichi (Mentor), Hirofumi Taguchi (Matsushita), Yasuhiro Tani (CANON), Ted Vucurevich (Cadence)