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ASP-DAC 2006 Archives
- 1A: Formal Methods for Coverage and Scalable Verification
- 1B: Interconnect for High-End SoC
- 1C: Timing Analysis and Optimization
- 1D: University Design Contest
- 2A: Software Techniques for Efficient SoC Design
- 2B: Application Examples with Leading Edge Design Methodology
- 2C: Placement
- 2D: Special Session: Electrothermal Design of Nanoscale Integrated Circuits
- 3A: Logic Synthesis
- 3B: Future Technical Directions for Design Automation
- 3C: Routing and Interconnect Optimization
- 3D: Special Session: Flash Memory in Embedded Systems
- 4A: Resolving Timing Issues: Design and Test
- 4B: Leading Edge Design Methodology for SoCs and SiPs
- 4C: Advanced Circuit Simulation
- 4D: Special Session: Open Access Overview
- 5A: Advances in Simulation Technologies
- 5B: Scheduling for Embedded Systems
- 5C: High Frequency Interconnect Effects in Nanometer Technology
- 5D: Designers' Forum: Low Power Design
- 6A: Power Optimization of Large-Scale Circuits
- 6B: Advanced Memory and Processor Architectures for MPSoC
- 6C: New Routing Techniques
- 6D: Designers' Forum Panel:Functional Verification -now and future
- 7A: Minimization of Test Cost and Power
- 7B: Substrate Coupling and Analog Synthesis
- 7C: Statistical and Yield Analysis
- 7D: Special Session: H.264/AVC Design Challenges and Solutions
- 8A: Floorplanning
- 8B: Memory Optimization for Embedded Systems
- 8C: Inductive Issues in Power Grids and Packages
- 8D: Designers' Forum: "Cell" Processor
- 9A: High-Level Synthesis
- 9B: Modeling, Compilation and Optimization of Embedded Architectures
- 9C: Statistical Design
- 9D: Designers' Forum Panel:Top 10 Design Issues by LSI Designers versus EDA Developers