Tutorials

Two full-day and four half-day tutorials will be presented in four parallel sessions on January 24, 2006. The tutorials are given by top experts in the fields and cover DFM, interconnect & packaging, low power, design verification and system level design, which are today's most important issues in system LSI design and EDA technologies.

  • New features of ASP-DAC2006 Tutorial
    • All-in-one textbook!
      • A textbook includes the materials for all the tutorials.
    • A lunch coupon is included.
  • Date: Tuesday, January 24, 2006 (9:30 - 17:00)
  • Place: Pacifico Yokohama, Conference Center, 4F

Time Title
Tutorial 1 (Full Day) 9.30 - 17.00 DFM Tools and Methodologies for 65nm and Below
Tutorial 2 (Full Day) 9.30 - 17.00 High performance interconnect and packaging
Tutorial 3 (Half Day) 9.30 - 12.30 Low Power / Low Leakage Technologies for Nanometer Era: System and Architecture Level Approaches
Tutorial 4 (Half Day) 14.00 - 17.00 Low Power / Low Leakage Technologies for Nanometer Era: Circuit and Device Level Approaches
Tutorial 5 (Half Day) 9.30 - 12.30 Basics and Practice of Current Functional Verification Methods
Tutorial 6 (Half Day) 14.00 - 17.00 SoC Communication Architectures: Current Practice, Research and Trends
  • Co-Chairs: Kazutoshi Wakabayashi (NEC Corporation), Chung-Kuan Cheng (University of California, San Diego)
  • Vice Chair: Hiroyuki Higuchi (FUJITSU LABORATORIES LTD.)

Tutorial 1 (Full Day), Tuesday, January 24, 9.30 - 17.00 (Room 411+412)

"DFM Tools and Methodologies for 65nm and Below"

Organizer:
Andrew B.Kahng - UCSD and Blaze DFM, Inc., United States

Speakers:
Andrew B.Kahng - UCSD and Blaze DFM, Inc., United States
Louis K.Scheffer - Cadence Design Systems, Inc., United States
Michael Orshansky - Univ. of Texas at Austin, United States
Andrzej Strojwas - PDF Solutions, Inc. and CMU, United States

Abstract:
This tutorial will present a view of key tool technologies and methodologies that are likely to become mainstream for the 65nm node and beyond. Topics include: (1) taxonomy of yield detractors and variability sources; (2) statistical extraction and performance analysis, (3) parametric yield optimizations for timing, power and reliability; (4) manufacturing simulations and analyses for shape (litho and etch), thickness (planarization), and defectivity (critical area); (5) manufacturing-aware capabilities in placement, routing, and post-route optimization tools; and (6) layout synthesis methodologies that range from restricted design rules to flexible layout and liquid libraries.

One word from Tutorial Chairs:
From the basics to practice of DFM. Lots of useful information based on real examples. We recommend this tutorial to engineers and researchers from both sides of design and manufacturing.

Tutorial 2 (Full Day), Tuesday, January 24, 9.30 - 17.00 (Room 413)

"High Performance Interconnect and Packaging"

Organizers:
Chung-Kuan Cheng - Univ. of California, San Diego, United States
Howard Chen - IBM, United States

Speakers:
Paul M. Harvey - IBM, United States
Howard Chen - IBM, United States
Chung-Kuan Cheng - Univ. of California, San Diego, United States
Manjit Borah - Fastrack, United States
Lei He - Univ. of California, Los Angeles, United States
Sheldon Tan - Univ. of California, Riverside, United States

Abstract:
With the advance of the VLSI technology, interconnect and packaging are becoming dominant factors in deciding system performance and power consumption. The scalability of interconnect and packaging is recognized as a principal challenge in ITRS Roadmap. This tutorial will provide an overview of new and emerging packaging and interconnect technologies and how they will impact silicon performance. A detailed discussion of the critical factors in the packaging and interconnect design that influence chip performance will be included. The tutorial will provide a comprehensive list of simple, often overlooked design methods to get the most out of many of today's most promising new packaging technologies.

One word from Tutorial Chairs:
Full of knowledge about interconnect&packaging-related issues and their solutions for high sillicon performance. These kinds of knowledge will become a must for system designers as well as logic and phisical designers from now on.

Tutorial 3 (Half Day), Tuesday, January 24, 9.30 - 12.30 (Room 414+415)

"Low Power / Low Leakage Technologies for Nanometer Era: System and Architecture Level Approaches"

Organizer:
Kimiyoshi Usami - Shibaura Institute of Technology, Japan

Speakers:
Naohiko Irie - Hitachi Ltd., Japan
Hiroshi Nakamura - Univ. of Tokyo, Japan

Abstract:
Energy-efficient design is strongly required in SoC's for portable applications. Even for high-end microprocessors, power dissipation becomes a critical hurdle when increasing the performance. This tutorial discusses technical challenges and approaches for low-power / low-leakage design at system and architecture levels. Topics include: dynamic voltage and frequency scaling (DVFS), queue resizing, pipeline balancing and scaling, cache and memory optimizations, globally asynchronous locally synchronous (GALS) architecture, trade-offs between power and reliability, etc.

One word from Tutorial Chairs:
(Tutorial 3 and 4) We are sure that the attendees of the two consecutive half-day tutorials for low power will obtain a total view of low power techniques from the architecture level to the circuit and device levels. Each half-day tutorial is self-contained so that registants can choose single one of the tutorials to combine with other half-day tutorials.

Tutorial 4 (Half Day), Tuesday, January 24, 14.00 - 17.00 (Room 414+415)

"Low Power / Low Leakage Technologies for Nanometer Era: Circuit and Device Level Approaches"

Organizer:
Kimiyoshi Usami - Shibaura Institute of Technology, Japan

Speakers:
Kimiyoshi Usami - Shibaura Institute of Technology, Japan
Tohru Mogami - NEC Corporation, Japan

Abstract:
Power dissipation is one of the most critical issues in nanometer devices. In addition to dynamic power, leakage power becomes a major concern. This tutorial discusses technical challenges and approaches for low-power / low-leakage design at circuit and device levels. Topics include: circuit and CAD techniques for power gating (MTCMOS), physical implementation and CAD techniques for multi-voltage design, high-k gate dielectric stucks, Cu/low-k interconnects, 3-D device structures, new materials such as SiGe, etc.

Tutorial 5 (Half Day), Tuesday, January 24, 9.30 - 12.30 (Room 416+417)

"Basics and Practice of Current Functional Verification Methods"

Organizer:
Kiyoharu Hamaguchi - Osaka Univ., Japan

Speakers:
Kiyoharu Hamaguchi - Osaka Univ., Japan
Erich Marschner - Cadence Design Systems, Inc., United States

Abstract:
This tutorial 1) summarizes basic concepts and currently available techniques in modern functional verification, 2) presents, in particular, practice of assertion-based verification, and 3) overviews advanced topics in formal verification methods.

[Part 1.] Basics of Functional Verification (Hamaguchi).
This part overviews currently available techniques in functional verification, which includes functional coverage, assertion, constrained random simulation and bounded/unbounded model checking. Rather than underlying algorithms of the techniques, we mainly discuss what can be done with the techniques from a point of designers' view.

[Part 2.] Practice of Assertion-Based Verification (Marschner).
This part presents various techniques for utilizing assertions and functional coverage monitors to achieve higher quality verification in less time. This includes guidelines for writing assertions and coverage monitors, recommendations for where to apply them, and how to leverage them most effectively in typical verification flows.

[Part 3.] Advanced Topics in Formal Functional Verification (Hamaguchi).
The last part introduces emerging techniques for functional validation or verification, which will be used in functional verification in near-future. This includes abstraction-refinement techniques for large-scale verification, and also formal verification techniques for high-level languages such as SpecC or UML.

One word from Tutorial Chairs:
All about modern functional verification. Assertion-based verification, formal verification, etc. have begun to be put into practical use. The audiences of this cource will learn how modern functional verification actually works and find hints to its further application to industrial design.

Tutorial 6 (Half Day), Tuesday, January 24, 14.00 - 17.00 (Room 416+417)

"SoC Communication Architectures: Current Practice, Research and Trends"

Organizer:
Nikil Dutt - Univ. of California, Irvine, United States

Speakers:
Nikil Dutt - Univ. of California, Irvine, United States
Sudeep Pasricha - Univ. of California, Irvine, United States

Abstract:
The increasing complexity of Systems-on-Chip (SoCs) has led to the critical ``design productivity gap'' problem. Several strategies are being employed to cope with this problem, including an IP-based design flow, as well as platform-based designs for application domains. These approaches have critically increased the amount of on-chip communication. Since on-chip communication architectures have a significant impact on system performance, power dissipation and time-to-market, system designers, as well as the research community have focused on the issue of exploring, evaluating, and designing SoC communication architectures to meet the targeted design goals. This tutorial will focus on the current design practices, research efforts and emerging trends in the area of on-chip communication architectures. In the first part of the tutorial, we will first motivate the need for a communication architecture-centric design flow for SoC designs. We will then present a survey of the communication architectures currently used in industry and discuss commonly used protocols and standards such as OCP-IP, VSIA, AMBA, CoreConnect, STBus and Sonics. This will be followed by a case study of a typical industrial design methodology that incorporates communication architecture design in their flow. In the second part of the tutorial, we will present a survey of research efforts in the area of communication architecture exploration, synthesis and implementation, with the goal of improving system performance, reducing power dissipation, cost and design cycle time. The focus of this part will be on variants of bus based and bus-matrix based communication architectures. In the final part of the tutorial, we will outline emerging trends in the area of on-chip communication architectures design and review research efforts on the topics of network-on-chips and on-chip optical interconnects.

One word from Tutorial Chairs:
A well-organized, introductory, but also practical, half-day-course of on-chip communication. Lots of current design examples. Full of useful information on commonly-used/standard bus architectures, communication-centril design methodology and hot topics like NoC.

Last Updated on: January 24, 2006