University LSI Design Contest Best Design Award
- Outstanding Design Award
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52mW 1200MIPS Compact DSP for Multi-Core Media SoC
Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting Kuo, Chie-Min Chao, Chih-Wei Liu (National Chiao Tung University, Taiwan)
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52mW 1200MIPS Compact DSP for Multi-Core Media SoC
- Special Feature Award
- A Low Dynamic Power and Low Leakage Power 90-nm CMOS Square-Root Circuit
Tadayoshi Enomoto, Nobuaki Kobayashi (Chuo University, Japan) -
Adaptively-Biased Capacitor-Less CMOS Low Dropout Regulator with Direct Current Feedback
Yat-Hei Lam, Wing-Hung Ki, Chi-Ying Tsui (Hong Kong University of Science and Technology, Hong Kong)
- A Low Dynamic Power and Low Leakage Power 90-nm CMOS Square-Root Circuit
University LSI Design Contest
The University LSI Design Contest is an important event of ASP-DAC, which focuses a real chip design in academia. The Design Contest Committee selected 19 designs for presentation, from which winners of design awards will be announced in the conference.
- Message from University LSI Design Contest Chairs
- Date: Wedneday, January 25, 2006
- Place: Pacifico Yokohama, Conference Center, 4F
- Oral Presentation: Room416+417 (10:15-12:20)
- Poster Presentation: Room 418 (12:20-13:30) (Food will be served.)
- Co-Chairs: Kazutoshi Kobayashi (Kyoto Univ., Japan), Takahiko Arakawa (Renesas, Japan)
- Design Contest Committee
Time | Title | ||
1D-1 | 10:15 - 10:20 | A Low Dynamic Power and Low Leakage Power 90-nm CMOS Square-Root Circuit | |
1D-2 | 10:20 - 10:25 | A 3D High-Throughput Low-Power Fully Parallel 1024-bit 1/2 Rate Low Density Parity Check Code Decoder | |
1D-3 | 10:25 - 10:30 | A 16-Bit, Low-Power Microsystem with Monolithic MEMS-LC Clocking | |
1D-4 | 10:30 - 10:35 | Ultra-Low Voltage Power Management Circuit and Computation Methodology for Energy Harvesting Applications | |
1D-5 | 10:35 - 10:40 | A 0.5-V Sigma-Delta Modulator Using Analog T-Switch Scheme for the Subthreshold Leakage Suppression | |
1D-6 | 10:40 - 10:45 | An Implementation of a CMOS Down-Conversion Mixer for GSM1900 Receiver | |
1D-7 | 10:45 - 10:50 | Integrated Direct Output Current Control Switching Converter using Symmetrically-Matched Self-Biased Current Sensors | |
1D-8 | 10:50 - 10:55 | Adaptively-Biased Capacitor-Less CMOS Low Dropout Regulator with Direct Current Feedback | |
1D-9 | 10:55 - 11:00 | A Built-in Power Supply Noise Probe for Digital LSIs | |
1D-10 | 11:00 - 11:05 | A 476-gate-count Dynamic Optically Reconfigurable Gate Array VLSI chip in a standard 0.35um CMOS Technology | |
1D-11 | 11:05 - 11:10 | Measurement Results of Within-Die Variations on a 90nm LUT Array for Speed and Yield Enhancement of Reconfigurable Devices | |
1D-12 | 11:10 - 11:15 | High-Throughput Decoder for Low-Density Parity-Check Code | |
1D-13 | 11:15 - 11:20 | Hardware Implementation of Super Minimum All Digital FM Demodulator | |
1D-14 | 11:20 - 11:25 | Designing a Custom Architecture for DCT Using NISC Design Flow | |
1D-15 | 11:25 - 11:30 | A 52mW 1200MIPS Compact DSP for Multi-Core Media SoC | |
1D-16 | 11:30 - 11:35 | Implementation of H.264/AVC Decoder for Mobile Video Applications | |
1D-17 | 11:35 - 11:40 | A High-Performance Platform-Based SoC for Informantion Security | |
1D-18 | 11:40 - 11:45 | Configurable Multi-Processor Architecture and its Processor Element Design | |
1D-19 | 11:45 - 11:50 | Design and Implementation of a Duplex AMBA-TMS Transducer |