Title | A Dual-MST Approach for Clock Network Synthesis |
Author | *Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham (Hong Kong Polytechnic Univ., Hong Kong), Fung-Yu Young (Chinese Univ. of Hong Kong, Hong Kong) |
Page | pp. 467 - 473 |
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Title | Buffered Clock Tree Sizing for Skew Minimization Under Power and Thermal Budgets |
Author | Krit Athikulwongse, *Xin Zhao, Sung Kyu Lim (Georgia Tech, U.S.A.) |
Page | pp. 474 - 479 |
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Slides |
Title | Critical-PMOS-Aware Clock Tree Design Methodology for Anti-Aging Zero Skew Clock Gating |
Author | Shih-Hsu Huang, Chia-Ming Chang, *Wen-Pin Tu, Song-Bin Pan (Chung Yuan Christian Univ., Taiwan) |
Page | pp. 480 - 485 |
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Slides |
Title | Clock Tree Embedding for 3D ICs |
Author | *Tak-Yung Kim, Taewhan Kim (Seoul National Univ., Republic of Korea) |
Page | pp. 486 - 491 |
Detailed information (abstract, keywords, etc) | |
Slides |