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The 15th Asia and South Pacific Design Automation Conference

Session 6A  Advances in Modern Clock Tree Routing
Time: 15:30 - 17:10 Wednesday, January 20, 2010
Location: Room 101A
Chairs: Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.), Tsung-Yi Ho (National Cheng Kung Univ., Taiwan)

6A-1 (Time: 15:30 - 15:55)
TitleA Dual-MST Approach for Clock Network Synthesis
Author*Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham (Hong Kong Polytechnic Univ., Hong Kong), Fung-Yu Young (Chinese Univ. of Hong Kong, Hong Kong)
Pagepp. 467 - 473
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6A-2 (Time: 15:55 - 16:20)
TitleBuffered Clock Tree Sizing for Skew Minimization Under Power and Thermal Budgets
AuthorKrit Athikulwongse, *Xin Zhao, Sung Kyu Lim (Georgia Tech, U.S.A.)
Pagepp. 474 - 479
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6A-3 (Time: 16:20 - 16:45)
TitleCritical-PMOS-Aware Clock Tree Design Methodology for Anti-Aging Zero Skew Clock Gating
AuthorShih-Hsu Huang, Chia-Ming Chang, *Wen-Pin Tu, Song-Bin Pan (Chung Yuan Christian Univ., Taiwan)
Pagepp. 480 - 485
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6A-4 (Time: 16:45 - 17:10)
TitleClock Tree Embedding for 3D ICs
Author*Tak-Yung Kim, Taewhan Kim (Seoul National Univ., Republic of Korea)
Pagepp. 486 - 491
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