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The 18th Asia and South Pacific Design Automation Conference

Session 9D  High-Level and Architectural Synthesis
Time: 16:00 - 18:00 Friday, January 25, 2013
Chairs: Robert Wille (Univ. of Bremen, Germany), Takashi Takenaka (NEC, Japan)

9D-1 (Time: 16:00 - 16:30)
TitleRange and Bitmask Analysis for Hardware Optimization in High-Level Synthesis
Author*Marcel Gort, Jason H. Anderson (Univ. of Toronto, Canada)
Pagepp. 773 - 779
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9D-2 (Time: 16:30 - 17:00)
TitleA Gradual Scheduling Framework for Problem Size Reduction and Cross Basic Block Parallelism Exploitation in High-level Synthesis
Author*Hongbin Zheng, Qingrui Liu, Junyi Li, Dihu Chen, Zixin Wang (Sun Yet-sen Univ., China)
Pagepp. 780 - 786
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9D-3 (Time: 17:00 - 17:30)
TitleImplementing Microprocessors from Simplified Descriptions
Author*Nikhil A. Patil, Derek Chiou (Univ. of Texas, Austin, U.S.A.)
Pagepp. 787 - 793
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9D-4 (Time: 17:30 - 18:00)
TitleApplication-Specific Fault-Tolerant Architecture Synthesis for Digital Microfluidic Biochips
Author*Mirela Alistar, Paul Pop, Jan Madsen (Denmark Technical Univ., Denmark)
Pagepp. 794 - 800
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