Designers' Forum

The Designers' Forum is a unique program that will share design experience and solutions of actual product designs of the industries. This year's program includes the invited talks on the advanced devices and networks for IoT applications, advanced automotive security, and advanced image sensing and processing. The forum also includes a panel discussion relating to the future of AI technologies.

  • Date: January 18-19, 2017
  • Place: Makuhari Messe, International Conference Hall, 1F, Room 103
  • Designers' Forum Chair: Masaitsu Nakajima (socionext)
  • Designers' Forum Chair: Koji Inoue (Kyushu University, Japan)

Date/Time Title
5S January 18, 13:50-15:30, Room 103 Oral Session:
Advanced Devices and Networks for IoT Applications
6S January 18, 15:50-17:30, Room 103 Panel Discussion:
What is future AI we will create ? - "Doraemon" or "Terminator" ? -
8S January 19, 13:50-15:30, Room 103 Oral Session:
Advanced Automotive Security
9S January 19, 15:50-17:30, Room 103 Oral Session:
Advanced Image Sensing and Processing

Session 5S: Wednesday, January 18, 13:50-15:30, Room 103

Oral Session: Advanced Devices and Networks for IoT Applications

Organizers: Koichiro Yamashita (Fujitsu Laboratories, Japan)
Tatsuo Shiozawa (Toshiba Corporation, Japan)
Masaru Kokubo (Hitachi Ltd., Japan)
Session Chair: Koichiro Yamashita (Fujitsu Laboratories, Japan)

In order to realize the system for various IoT applications, it must be considered the overall element technologies from the sensor-front to the cloud via the network. In this session, for the specified concrete IoT applications, it will introduce a distinctive technology to realize it. In details, the first presentation of this session describes an autonomous mesh networking technology that allows a maintenance-free deployment of the sensor node for the infrastructural monitoring system. The second is the small, high-performance and low-power CPU technology for the wearable devices used in the wellness applications. The third is the ultra-low-power circuit techniques for energy-harvesting which realizes a millimeter-size sensors strewn as a dust computing applications. The final presentation is DFS (dynamic frequency selection) technology that is an advanced network devices to communicate the huge amount of data generated from a various IoT applications.

  • 1: Implementation of Reliable and Maintenance-Free Wireless Multihop Networks

    Ren Sakata, Suhwuk Kim, Hiroki Kudo (Toshiba Corporation, Japan)

    Wireless sensor networks have recently attracted attention since these are able to realize continuous observation of old infrastructures such as bridges and tunnels. Even places requiring long-term observation for detecting structural deterioration can be monitored simply by attaching a sensor. In this presentation, a prototype of a maintenance-free sensor node is introduced. They key features of this technology are the autonomous formation of a mesh network and achievement of low power consumption. Without the use of special settings, each wireless sensor autonomously recognizes ambient conditions, adjusts the timing of communications and forms a communication network with neighboring sensors. The network also minimizes standby power based on communication conditions, so that wireless communication can be maintained for long periods using batteries alone. This maintenance-free system reliably collects sensor data across a wide area.

  • 2: High-performance and Low-power Embedded Memory for Edge Computing System

    Masami Nakajima (Renesas Electronics Corporation, Japan)

    In the future's edge computing system, we need to reduce the size and weight while maintaining high performance. It is necessary to provide 100-200MHz performance to CPU. Also, we must reduce the size of the battery, which is largest and heaviest parts of all. Therefore, low power is necessary. In this work, by using high-performance and low-power embedded flash technology and the low-power memory access scheme which includes low-voltage bus architecture and automatic power on/off scheme, we have succeeded in reducing power consumption with high computing power.

  • 3: Ultra-low-power wireless sensor nodes with energy harvesting, and IoT gateway technology

    Hiroki Morimura (NTT Corporation, Japan)

    Ultra-low-power circuit techniques for energy-harvesting and IoT gateway technology for connecting various sensors are described. Power generated by energy harvester becomes as small as the nanowatt level when the size of a sensor node becomes millimeter-size. The portfolio of energy harvesting and circuit technology is discussed from the viewpoints of technical and application issues. Then, nanowatt level wireless circuit techniques are explained. Moreover, the concept of IoT gateway technology in order to improve “connectivity” for gathering huge data will be presented.

  • 4: Fast Channel Switching Technique for Interference Avoidance with 5 GHz Dual Channel Wireless LAN

    Takashi Takeuchi (Hitachi Ltd., Japan)

    In 5 GHz wireless LAN, a DFS (dynamic frequency selection) technology must be implemented to avoid interference from radars. However, in accordance with Japanese regulations, communication is interrupted for 60 seconds by the radar scan after communication frequency switches. We addressed this challenge by developing a novel wireless access point possessing two RF modules. Preparing another channel in the access point enables fast and stable frequency switching at the initiative of a station. Measurement results of the prototype system showed a frequency switching delay time of 11 milliseconds under the DFS environment.

Session 6S: Wednesday, January 18, 15:50-17:30, Room 103

Panel Discussion: What is future AI we will create? – "Doraemon" or "Terminator" ? –

Organizers: Hiroe Iwasaki (NTT, Japan)
Sunao Trii (ExaScaler, Japan)
Akihiko Inoue (Panasonic, Japan)

Nowadays, Artificial Intelligence (AI) research and development is in third boom. The driving force behind this advancement is deep learning technology. Its high level feature extraction ability was adopted in AI GO application "AlphaGO", and accomplished a great feat that AlphaGO overthrow human champion. But emergence of strong AI is now stirring up controversy simultaneously. Our job is just maybe replaced with AI power !!
Is it true? What should we do, if autonomous AI has consciousness and has hostility toward human? These concerns is too excessive assumption, but we cannot ignore. So, in this panel session, we will discuss about real situation of current AI and think about future AI. Key word is "Doraemon" and "Terminator".

Moderator:Satoshi Kurihara (The University of Electro-Communications, Japan)
Panelists: Hiroshi Yamakawa (dwango)
Luca Rigazio (Panasonic Silicon Valley Lab)
Takeshi Yamada (NTT)
Akira Naruse (NVIDIA)
Shinji Nakadai (NEC)

Session 8S: Thursday, January 19, 13:50-15:30, Room 103

Oral Session: Advanced Automotive Security

Organizers: Shinichi Shibahara (Renesas System Design, Japan)
Akihiko Inoue (Panasonic, Japan)
Session Chair: Shinichi Shibahara (Renesas System Design, Japan)

The security implementation for automotive is getting hot and essential toward autonomous driving. This session will visit its trend, hardware implementation, hardware attack and its countermeasure. The first talk presents recent threats in automotive systems and their countermeasures with security applications. The next presentation shows the actual implementation of hardware security module for microcontrollers. The third one demonstrates the hardware attack experience in academia and proposes the key management method. The final talk shares physical and logical attacks previously being used for smart card and their countermeasures.

  • 1: Using Security Applications for Automotive Hardware Security Modules

    Dennis Kengo Oka (ETAS, Japan)

    With advancements in connectivity and new technologies, the attack surface for automotive systems is increasing. Various new cybersecurity threats are emerging that can have major safety and financial impacts. As a result, it is imperative to understand these threats to apply the appropriate security measures. This talk will present a number of threats and discuss how such threats can be countered using security applications for automotive hardware security modules.

  • 2: An Embedded Hardware Security Module for Automotive ECUs

    Yasuhisa Shimazaki (Renesas Electronics Corporation, Japan)

    In coming autonomous-driving era, automobiles and many kinds of facilities will be connected each other to provide safe, comfortable and efficient driving environment for drivers. Vehicle to vehicle communication, for example, is necessary to get some safety-related information such as distance, speed, and condition of the neighbors, or communication between a vehicle and cloud is used to obtain traffic information, to update firmware of electronic control units (ECUs), and so forth. This means, however, we need to pay much attention to micro controller unit (MCU) design in terms of cyber security. In 2015, actually, remote attack for a running car through cellular network was demonstrated, resulting in 1.4 million recalls. In order to address this issue, MCUs need to have some sort of security measures which protect themselves and their communication channels effectively and efficiently. Based on this motivation, we have implemented a hardware security module on our MCUs. In this presentation, actual implementation of the hardware security module that supports SHE and EVITA, which are widely accepted security specifications for automotive applications, will be shown. The presentation will also cover performance evaluation results of elliptic curve digital signature algorithm (ECDSA) verification used in vehicle to x (V2X) communication.

  • 3: Security Hardware for Automotive Applications

    Takeshi Fujino (Ritsumeikan University, Japan)

    Several kinds of malicious attacks against vehicles have been demonstrated in the past few years. The first one since 2010 is an invasive attack to the in-vehicle CAN network. The speed-meters on the dashboard can be wrongly displayed, and some equipments such as windshield wiper or turn signal can be controlled by the command injected from the PC via ODB-II port. The next stage is a remote attack from cellular network, where abnormal operations of accelerator and engine are demonstrated on Jeep in 2015. FCA issued a recall for 1.4 million vehicles on a vulnerable software. In future, the authenticated CAN communication and ECUs with secure-boot sequence will be deployed against these attacks, however, secure key management and storage on ECUs are problems to be solved. We proposed the key management method using tamper resistant AES cryptographic circuit and PUF. The latest attack targets are ADAS sensors such as sonar, radar, and camera. After the vulnerability reports presented by some security researchers including us, the demonstration, where the auto-pilot system on Tesla’s car is easily fooled, was reported in the summer of 2016. The development of tamper-resistant ADAS sensors will be important for the future self-driving car.

  • 4: Physical and Logical Attacks against LSI Chips and Their Countermeasures

    Shinichi Kawamura (Toshiba Corporation, Japan)

    Since the proposal of a timing attack and a power analysis in mid 90s, physical and logical attacks against LSI chips are one of the most critical issues in the research of crypto implementation and the smart card industry. Since LSI for smart card is almost bare, it is not difficult for attackers to make direct access to the controller. In the smart card industry, however, a validation program and testing laboratories have been established and are working well to prevent a critical incident. It is now expected that controllers of automobile are the next critical target of such attacks. Unlike the case of smart card, attack to LSI chip of an automobile controller would be directly connected to the loss of a human life. Therefore, we have to be serious to learn from the cases in smart card industry as to how we should prepare against such threats.

Session 9S: Thursday, January 19, 15:50-17:30, Room 103

Oral Session: Advanced Image Sensing and Processing

Organizers: Yusuke Oike (Sony Semiconductor Solutions, Japan)
Masaitsu Nakajima (Socionext, Japan)
Session Chair: Yusuke Oike (Sony Semiconductor Solutions, Japan)

Four advanced design examples of image sensors and processors are described. For designing better image quality and intelligent functionality on image sensing and processing, this session covers circuit techniques on analog-to-digital conversion, 3-D stacked device integration, system architecture integrating computational vision, and FPGA implementation efficiently accelerating partial image retrieval. The first talk presents a 250M-pixel CMOS image sensor employing column-parallel dual-gain amplifiers, followed by a back- illuminated stacked CMOS image sensor achieving multi-functional modes. The third presentation forecasts the next trend on machine vision beyond human eyes. The final talk demonstrates an FPGA-accelerated partial image-matching engine for massive media-data searching systems.

  • 1: An APS-H-Size 250Mpixel CMOS Image Sensor Using Column Single-Slope ADCs with Dual-Gain Amplifiers

    Hirofumi Totsuka (Canon, Japan)

    This talk presents an APS-H size 250Mpixel CMOS image sensor. The sensor is fabricated with a 0.13μm CMOS technology and is based on 1.5μm-pitch pixels and single-slope column ADCs with dual-gain amplifiers featuring 6dB wider dynamic range and 75% shorter conversion time than a conventional single-slope ADC.

  • 2: A 1/1.7-inch 20Mpixel Back-Illuminated Stacked CMOS Image Sensor

    Chihiro Okada (Sony Semiconductor Solutions, Japan)

    This talk presents a 1/1.7-inch 20Mpixel back-illuminated stacked CMOS image sensor with multifunctional modes which are parallel multiple sampling, the two simultaneous output streams and data compression. This sensor has achieved a RMS random noise of 1.3e- with the parallel multiple sampling and the two simultaneous output streams of 4Mpixel for a movie mode and 16Mpixel for a still mode with a 2.3Gb/s/lane high-speed interface. Furthermore, the high speed output mode of 16Mpixel at 120fps with a low image degradation compression. The stacked structure realizes on an analog implementation of the double column parallel ADCs.

  • 3: Emerging Applications based on High-speed Computational Vision

    Yoshihiro Watanabe (The University of Tokyo, Japan)

    High-speed computational vision can simultaneously execute not just image capturing and recording but also image processing at the level of 1,000 fps. This system is expected to open up emerging applications in various fields. This presentation gives an overview of the system architectures, the image processing, and the image sensing technologies, and the actual application examples such as high-speed digital archiving and interactive display systems.

  • 4: Acceleration of Partial Image Matching on FPGA Platforms using OpenCL

    Noboru Yoneoka (Fujitsu Laboratories, Japan)

    The increasing amount of data such as presentation materials and visualized documents leads to high demand for efficient document search systems. In this presentation, we introduce a visual document search system with partial image matching engine accelerated on FPGA. The FPGA accelerator is developed in OpenCL environment which makes highly efficient description of FPGA hardware and software. With task parallelization and a data pipeline architecture, the system provides high throughput performance and quick response.

Last Updated on: 10 21, 2016