University LSI Design Contest

The University LSI Design Contest has been conceived as a unique program at ASP-DAC. The purpose of the contest is to encourage research in LSI design at universities and its realization on a chip by providing opportunities to present and discuss the innovative and state-of-the-art design. The scope of the contest covers circuit techniques for (1) Analog / RF / Mixed-Signal Circuits, (2) Digital Signal Processer, (3) Microprocessors, and (4) Custom Application Specific Circuits / Memories, and methodologies for (a) Full-Custom / Cell-Based LSIs, (b) Gate Arrays, and (c) Field Programmable Devices.

This year, the University LSI Design Contest Committee received 25 designs from five countries/areas, and selected 20 designs out of them. The selected designs will be disclosed in Session 1S at three-minute presentations, followed by interactive discussions in front of their posters with light meals. For two outstanding designs, The Best Design Award and The Special Feature Award will be presented in the opening session. We sincerely acknowledge the other contributions to the contest, too. It is our earnest belief to promote and enhance research and education in LSI design in academic organizations. Please come to the University LSI Design Contest and enjoy the stimulating discussions.

  • Date: Tuesday, January 17, 2017
  • Place: Makuhari Messe International Convention Complex, International Conference Hall, 1F
    • Oral Presentation : TBA (11:05-12:20)
    • Poster Presentation : TBA
  • Co-chairs: Hiroyuki Ito (Tokyo Institute of Technology), Noriyuki Miura (Kobe University)
  • University LSI design contest committee
  • UDC Session Schedule (html-version)
Title
1S-1 W-Band Ultra-High Data-Rate 65nm CMOS Wireless Transceiver
1S-2 An Image Sensor/Processor 3D Stacked Module featuring ThruChip Interfaces
1S-3 A 686Mbps 1.85mm2 Near-Optimal Symbol Detector for Spatial Modulation MIMO Systems in 0.18um CMOS
1S-4 A Scalable Time-Domain Biosensor Array Using Logarithmic Cyclic Time-Attenuation-Based TDC for High-Resolution and Large-Scale Bio-Imaging
1S-5 An HDL-Synthesized Injection-Locked PLL Using LC-Based DCO for On-chip Clock Generation
1S-6 A 14bit 80kSPS Non-Binary Cyclic ADC without High Accuracy Analog Components
1S-7 Non-Binary Cyclic ADC with Correlated Level Shifting Technique
1S-8 A Current-Integration-Based CMOS Amperometric Sensor with 1.2μm x 2.05μm Electroless-Plated Microelectrode Array for High-Sensitivity Bacteria Counting
1S-9 A Real-time 17-Scale Object Detection Accelerator with Adaptive 2000-Stage Classification in 65nm CMOS
1S-10 A 15 x 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout
1S-11 Design of an Energy-Autonomous Bio-Sensing System Using a Biofuel Cell and 0.19V 53μW Integrated Supply-Sensing Sensor with a Supply-Insensitive Temperature Sensor and Inductive-Coupling Transmitter
1S-12 A 13.56MHz CMOS Active Diode Full-Wave Rectifier Achieving ZVS with Voltage-Time-Conversion Delay-Locked Loop for Wireless Power Transmission
1S-13 CMOS-on-Quartz Pulse Generator for Low Power Applications
1S-14 A 13.56 MHz On/Off Delay-Compensated Fully-Integrated Active Rectifier for Biomedical Wireless Power Transfer Systems
1S-15 A Wireless Power Receiver with a 3-Level Reconfigurable Resonant Regulating Rectifier for Mobile-Charging Applications
1S-16 Sub-1-μs Start-up Time, 32-MHz Relaxation Oscillator for Low-Power Intermittent VLSI Systems
1S-17 A 19-uA Metabolic Equivalents Monitoring SoC using Adaptive Sampling
1S-18 An FPGA-Compatible PLL-Based Sensor against Fault Injection Attack
1S-19 Variability Mapping at Runtime Using the PAnDA Multi-reconfigurable Architecture
1S-20 Design of High-Frequency Piezoelectric Resonator-Based Cascaded Fractional-N PLL with Sub-ppb-Order Channel Adjusting Technique
Last Updated on: 2016年11月 5日