University LSI Design Contest

The University LSI Design Contest has been conceived as a unique program at ASP-DAC. The purpose of the contest is to encourage research in LSI design at universities and its realization on a chip by providing opportunities to present and discuss the innovative and state-of-the-art design. The scope of the contest covers circuit techniques for (1) Analog / RF / Mixed-Signal Circuits, (2) Digital Signal Processer, (3) Microprocessors, and (4) Custom Application Specific Circuits / Memories, and methodologies for (a) Full-Custom / Cell-Based LSIs, (b) Gate Arrays, and (c) Field Programmable Devices.

This year, the University LSI Design Contest Committee received 15 designs from five countries/areas, and selected 13 designs out of them. The selected designs will be disclosed in Session 1A at three-minute presentations, followed by interactive discussions in front of their posters with light meals. For three outstanding designs, The Best Design Award and The Special Feature Awards will be presented in the opening session. We sincerely acknowledge the other contributions to the contest, too. It is our earnest belief to promote and enhance research and education in LSI design in academic organizations. Please come to the University LSI Design Contest and enjoy the stimulating discussions.

Title
1A-1 A Wide Conversion Ratio, 92.8% Efficiency, 3-Level Buck Converter with Adaptive On/Off-Time Control and Shared Charge Pump Intermediate Voltage Regulator
1A-2 A Three-Dimensional Millimeter-Wave Frequency-Shift Based CMOS Biosensor using Vertically Stacked Spiral Inductors in LC Oscillators
1A-3 Design of 385 x 385 µm2 0.165V 270pW Fully-Integrated Supply-Modulated OOK Transmitter in 65nm CMOS for Glasses-Free, Self-Powered, and Fuel-Cell-Embedded Continuous Glucose Monitoring Contact Lens
1A-4 2D Optical Imaging Using Photosystem I Photosensor Platform with 32×32 CMOS Biosensor Array
1A-5 Design of Gate-Leakage-Based Timer Using an Amplifier-Less Replica-Bias Switching Technique in 55-nm DDC CMOS
1A-6 A Low-Voltage CMOS Electrophoresis IC Using Electroless Gold Plating for Small-Form-Factor Biomolecule Manipulation
1A-7 A Low-Voltage Low-Power Multi-Channel Neural Interface IC Using Level-Shifted Feedback Technology
1A-8 Development of a High Stability, Low Standby Power Six-Transistor CMOS SRAM Employing a Single Power Supply
1A-9 Design of Heterogeneously-integrated Memory System with Storage Class Memories and NAND Flash Memories
1A-10 A 65-nm CMOS Fully-Integrated Circulating Tumor Cell and Exosome Analyzer Using an On-Chip Vector Network Analyzer and a Transmission-Line-Based Detection Window
1A-11 Low Standby Power CMOS Delay Flip-Flop with Data Retention Capability
1A-12 Accelerate Pattern Recognition for Cyber Security Analysis
1A-13 FPGA Laboratory System supporting Power Measurement for Low-Power Digital Design
Last Updated on: October 12, 2018