Preparation Guide for Technical Paper Submission

Paper Submission for Review was Closed.

The submission deadlines are set based on Japan Standard Time (JST). JST goes ahead of most other local times. The deadline by local times is as follows:

  • 7/20 1:00 @ San Jose
  • 7/20 4:00 @ New York
  • 7/20 9:00 @ London
  • 7/20 10:00 @ Paris, Munich
  • 7/20 13:30 @ New Delhi
  • 7/20 16:00 @ Beijing, Taipei
  • 7/20 17:00 @ Tokyo, Seoul
  • 7/20 18:00 @ Sydney

Key Dates:

  • Deadline for submission: July 20 (Wed), 2005 (17:00, JST)
  • Notification of acceptance: September 30 (Fri), 2005
  • Deadline for final version: November 18 (Thu), 2005

Instructions

In order to submit your paper, please follow the instructions below.

1) Paper preparation

  • Initial manuscripts should NOT include authors' names and their affiliations in order to perform a blind review. Authors' names, their affiliations and the contact person are requested when you submit your paper via the paper submission system.


  • The paper should be between 3 to 6 pages in length including all figures, tables and references. The technical expositions will be reviewed by specialists but should include an introduction for nonspecialists that describes the problem and achieved results, focusing on the important ideas and their significance.


  • Accepted file format is PDF only. No other formats will be accepted. You must make a pdf file which can be read by Acrobat Reader 5.0. Manuscripts should not include special fonts such as Asian fonts.


  • The paper for initial submission is to be formated like this (LaTex, LaTex2e). You can get the templates of initial sumission for (LaTex), (LaTex2e), and (MSWord).


2) Paper Submission

  • Paper Submission was closed.

Requirement

  • All accepted papers should be presented at the conference.
  • Dual submission with other conferences is not allowed.

Remarks:

  • Papers will be accepted for publication as either of regular papers or short papers. The paper type ** cannot ** be chosen by authors when submitting papers.
  • Papers may need to be shortened after acceptance, depending on the paper type. The page limit for short papers will be four.

Area of Interest:

Original, unpublished works on, but not limited to, the following areas are invited.

[1] System Level Design Methodology:
System VLSI and SOC design methods, System specification, Specification languages, Design languages, Design reuse and IPs, Platform-based design, Network on chip design
[2] Embedded and Real-Time Systems:
Hardware-software co-design, Co-simulation, Co-verification, Real-time OS and middleware, Design language for embedded systems, Compilation techniques, ASIP synthesis
[3] Behavioral/Logic Synthesis and Optimization:
Behavioral/RTL synthesis, Technology independent optimization, Technology mapping, Interaction between logic design and layout, Sequential and asynchronous logic synthesis
[4] Validation and Verification for Behavioral/Logic Design:
Logic simulation, Symbolic simulation, Formal verification, Equivalence checking, Transaction-level/RTL and gate level modeling and validation
[5] Physical Design (Routing):
Routing, Repeater issues, Interconnect optimization, Interconnect planning, Module generation, Layout verification
[6] Physical Design (Placement):
Placement, Floorplanning, Partitioning, Hierarchical design
[7] Timing, Power, Signal/Power Integrity Analysis and Optimization:
Timing analysis, Power analysis, Signal/power integrity, Clock and global signal design
[8] Interconnect, Device and Circuit Modeling and Simulation:
Interconnect modeling, Interconnect extraction, Package modeling, Circuit simulation, Device modeling/simulation, Library design, Design fabrics, Design for manufacturability, Yield optimization, Reliability analysis, Emerging technologies
[9] Test and Design for Testability:
Test design, Fault modeling, ATPG, BIST and DFT, Memory, core and system test
[10] Analog, RF and Mixed Signal Design and CAD:
Analog/RF synthesis, Analog layout, Verification, Simulation techniques, Noise analysis, Analog circuit testing, Mixed signal design
[11] Leading Edge Design Methodology for SOCs and SIPs:
Microprocessors, DSP, IP-core design, Design for multimedia, Design for wireless communication, A/D mixed circuits, Memories, Sensors, MEMS chips, FPGA design, Novel reconfigurable systems, Rapid prototyping

Inquiry

For more information, please contact: aspdac06papers@vlsi.kuee.kyoto-u.ac.jp

Technical Program Chair
Hidetoshi Onodera

Technical Program Vice Chair
Yusuke Matsunaga

Last Updated on: July 21, 2005