Session 2D: Special Session - Tackling Manufacturability/Variability for 32nm and Below

2D-1

Title	(Invited Paper) Lithography Challenges and Solutions for 32nm Node and Beyond
Author	*Yao-Ching Ku (TSMC, Taiwan)
No Slides

2D-2

Title	(Invited Paper) Predictive Models and CAD Methodology for Pattern Dependent Variability
Author	*Nishath Verghese, Richard Rouse, Philippe Hurat (Cadence Design Systems, USA)
Abstract	Lithography, etch and stress are dominant effects impacting the functionality and performance of designs at 65nm and below. This paper discusses pattern dependent variability caused by these effects and discusses a modelbased approach to extracting this variability. A methodology to gauge the extent of this pattern dependent variability for standard cells is presented by looking at the difference in transistor parameters when the cell is analyze in different contexts. A full-chip methodology that addresses the delay change due to systematic varation has been introduced to analyze and repair a 65nm digital design.
No Slides

2D-3

Title	(Invited Paper) Technology Modeling and Characterization Beyond the 45nm Node
Author	*Sani R. Nassif (IBM, USA)
No Slides

2D-4

Title	(Invited Paper) Synergistic Physical Synthesis for Manufacturability and Variability in 45nm Designs and Beyond
Author	*David Z. Pan, Minsik Cho (Univ. of Texas, Austin, USA)
Abstract	Nanometer IC designs are increasingly challenged by manufacturing closure, i.e., being fabricated with high product yield, mainly due to aggressive technology scaling and increasing process/environmental variations. Realizing the criticality of addressing manufacturability for higher yield and tolerance to variations during design, there has been a surge of research activities recently from both academia and industry. In this paper, we will survey the key activities in synergistic physical synthesis and shed lights on some of the future research directions.
No Slides

Last Updated on: January 31, 2008