Designers' Forum
- Date: January 23 ~ 24, 2008
- Place: COEX, Room 311BC
- Designers' Forum Chair: Hyunchul Shin (Hanyang Univ.)
4D: Wednesday, January 23, 10:15-12:20, Room 311BC
New Emerging Application Areas for Future SoC
Chair: |
Sungjoo Yoo (Samsung Electronics, Korea) |
Speakers: |
JuneHee Lee (Samsung Electronics, Korea) Shorin Kyo (NEC, Japan) Doug Pulley (picoChip , UK) Tatsuo Nakagawa (Hitachi, Japan) |
5D: Wednesday, January 23, 13:30-15:35, Room 311BC
Are System Level EDA Tools/Methodologies Coming?
Moderator: |
Ren-Song Tsay (Nat'l Tsing Hua Univ., Taiwan) |
Panelists: |
Raul Camposano (Xoomsys, USA) Toshihiro Hattori (Renesas Technology, Japan) Austin Kim (Samsung Electronics, Korea) Sri Parameswaran (Univ. of New South Wales, Australia) |
8D: Thursday, January 24, 13:30-15:35, Room 311BC
Low Power Chips
Chair: |
Kang Yi (Handong Global Univ., Korea) |
Speakers: |
T. W. Williams (Synopsys, USA) Hiroaki Shikano (Hitachi, Japan) Hock Chen (Global Unichip, Taiwan) Shuichi Kunie (NEC, Japan) |
9D: Thursday, January 24, 15:50-17:55, Room 311BC
Best Ways to Use Billions of Devices on a Chip
Moderator: |
Grant Martin (Tensilica , USA) |
Panelists: |
Deming Chen (Univ. of Illinois, Urbana-Champaign, USA) Nikil Dutt (Univ. of California, Irvine, USA) Joerg Henkel (Karlsruhe Univ., Germany) Kyungho Kim (Samsung Electronics, Korea) Kazutoshi Kobayashi (Kyoto Univ., Japan) |