| No. |
Paper Title |
Author |
Affiliation |
Country |
| 1 |
High-Level Power Management Considering DC-DC Converter Efficiency |
Yongseok Choi |
Seoul Nat'l Univ. |
Korea |
| 2 |
Post-Silicon Clock-timing Tuning with the Discrete PDE Delay Value |
Yuko Hashizume |
The Univ. of Kitakyushu |
Japan |
| 3 |
xTune: Model-Based Online Verifiable Cross-Layer Adaptation for Distributed Real-Time Embedded Systems |
Minyoung Kim |
Univ. of California, Irvine |
USA |
| 4 |
Convex Optimization to Fixed-Outline Floorplanning |
Chaomin Luo |
Univ. of Waterloo |
Canada |
| 5 |
Instruction Scheduling for Processors with Partial Forwarding |
Takuji Hieda |
Osaka Univ. |
Japan |
| 6 |
A Low Power ASIP Generation Method by Means of Extracting Non-redundant Activation Conditions |
Hirofumi Iwato |
Osaka Univ. |
Japan |
| 7 |
PSM-aware Layout Modification Techniques |
Ming-Chao Tsai |
Nat'l Tsing-Hua Univ. |
Taiwan |
| 8 |
A 10b 120MS/s 0.18um CMOS Pipeline A/D Converter Based on a Supply-Insensitive CMOS Reference Circuit |
Seung-Hoon Lee |
Sogang Univ. |
Korea |
| 9 |
Research on Current-Mode Differential Logic |
Ling Zhang |
Univ. of California, San Diego |
USA |
| 10 |
Interconnect Synthesis and Optimization Using Algorithmic Approaches |
Yi Zhu |
Univ. of California, San Diego |
USA |
| 11 |
Reducing the Dynamic Energy Consumption in the Multi-Layer Memory of Embedded Signal Processing Applications |
Ilie Luican |
Southern Utah Univ. |
USA |
| 12 |
Fast Routing Pattern Design for 2-layer Ball Grid Array Packages |
Yoichi Tomioka |
Tokyo Inst. of Tech. |
Japan |
| 13 |
Core-Based Testing of System-on-Chips Utilizing the Network-on-Chip Resources |
Fawnizu Azmadi Hussin |
Nara Inst. of Science and Technology |
Japan |
| 14 |
Typical-case Design Methodology: Concept, Challenge, and Case Study |
Yuji Kunitake |
Kyushu Inst. of Tech. |
Japan |
| 15 |
Efficient Behavioral Synthesis from Large Sequential Programs |
Yuko Hara |
Nagoya Univ. |
Japan |
