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The 16th Asia and South Pacific Design Automation Conference

Session 2C  Modeling for Signal and Power Integrity
Time: 13:40 - 15:40 Wednesday, January 26, 2011
Location: Room 414+415
Chairs: Hideki Asai (Shizuoka Univ., Japan), Kimihiro Ogawa (STARC, Japan)

2C-1 (Time: 13:40 - 14:10)
TitleA Fast Approximation Technique for Power Grid Analysis
Author*Mysore Sriram (Intel Corp., India)
Pagepp. 171 - 175
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2C-2 (Time: 14:10 - 14:40)
TitleEquivalent Lumped Element Models for Various n-Port Through Silicon Vias Networks
Author*Khaled Salah Mohamed (Mentor Graphics, Egypt), Hani Ragai (Ain-Shams Univ., Egypt), Yehea Ismail (Nile Univ., Egypt), Alaa El Rouby (Mentor Graphics, Egypt)
Pagepp. 176 - 183
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2C-3 (Time: 14:40 - 15:10)
TitleClock Tree Optimization for Electromagnetic Compatibility (EMC)
Author*Xuchu Hu, Matthew R. Guthaus (Univ. of California, Santa Cruz, U.S.A.)
Pagepp. 184 - 189
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2C-4 (Time: 15:10 - 15:40)
TitlePulser Gating: A Clock Gating of Pulsed-Latch Circuits
Author*Sangmin Kim, Inhak Han, Seungwhun Paik, Youngsoo Shin (KAIST, Republic of Korea)
Pagepp. 190 - 195
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