| Title | Path Criticality Computation in Parameterized Statistical Timing Analysis |
| Author | *Jaeyong Chung (University of Texas at Austin, U.S.A.), Jinjun Xiong, Vladimir Zolotov (IBM Thomas J. Watson Research Center, U.S.A.), Jacob A. Abraham (University of Texas at Austin, U.S.A.) |
| Page | pp. 249 - 254 |
| Keyword | Criticality probability, Statistical timing, Parametric variation |
| Abstract | This paper presents a method to compute criticality probabilities of paths in parameterized statistical static timing analysis (SSTA). We partition the set of all the paths into several groups and formulate the path criticality into a joint probability of inequalities. Before evaluating the joint probability directly, we simplify the inequalities through algebraic elimination, handling topological correlation. Our proposed method uses conditional probabilities to obtain the joint probability, and statistics of random variables representing process parameters are changed due to given conditions. To calculate the conditional statistics of the random variables, we derive analytic formulas by extending Clark's work. This allows us to obtain the conditional probability density function of a path delay, given the path is critical, as well as to compute criticality probabilities of paths. Our experimental results show that the proposed method provides 4.2X better accuracy on average in comparison to the state-of-art method. |
| Slides |
| Title | Run-Time Adaptable On-Chip Thermal Triggers |
| Author | *Pratyush Kumar, David Atienza (EPFL, Switzerland) |
| Page | pp. 255 - 260 |
| Keyword | DTM, Neural network, Predictive |
| Abstract | With ever-increasing power densities, Dynamic Thermal Management (DTM) techniques have become mainstream in today’s systems. An important component of such techniques is the thermal trigger. It has been shown that predictive thermal triggers can outperform reactive ones [4]. In this paper, we present a novel trade-off space of predictive thermal triggers, and compare different approaches proposed in the literature. We argue that run-time adaptability is a crucial parameter of interest. We present a run-time adaptable thermal simulator compatible with arbitrary sensor configuration based on the Neural Network (NN) simulator presented in [14]. We present experimental results on Niagara UltraSPARC T1 chip with real-life benchmark applications. Our results quantitatively establish the effectiveness of the proposed simulator for reducing (by up to 90%), the otherwise unacceptably high errors, that can arise due to expected leakage current variation and design-time thermal modeling errors. |
| Slides |
| Title | Rethinking Thermal Via Planning with Timing-Power-Temperature Dependence for 3D ICs |
| Author | Kan Wang, *Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong (Tsinghua University, China), Jason Cong (University of California, Los Angeles, U.S.A.) |
| Page | pp. 261 - 266 |
| Keyword | Thermal Via, Leakage Power, Delay, Timing-Power-Temperature Dependence |
| Abstract | Due to the increased power density and lower thermal conductivity, 3D is faced with heat dissipation and temperature problem seriously, which become a bottleneck in 3D circuit design. Previous researches showed that leakage power and delay are both relevant to temperature, and increase as the temperature increases. The timing-power-temperature dependence will potentially negate the performance improvement of 3D designs. TSV (Through-silicon-vias) has been shown as an effective way to help the heat removal, but they create routing congestions. Therefore, how to reach the trade-off between temperature, via number and delay is required to be solved. Different from previous works on TSV planning which ignored the effects of leakage power, in this paper, we integrate temperature-leakage-timing dependence into thermal via planning of 3D ICs. A weighted via insertion approach, considering both performance and heat dissipation with resource constraint, is proposed to achieve the best balance among delay, via number and temperature. |
| Slides |
| Title | The Impact of Inverse Narrow Width Effect on Sub-threshold Device Sizing |
| Author | Jun Zhou, *Senthil Jayapal, Jan Stuyt, Jos Huisken, Harmke de Groot (Holst Centre/IMEC, Netherlands) |
| Page | pp. 267 - 272 |
| Keyword | sub-threshold, sizing, inverse narrow width effect |
| Abstract | We have investigated the impact of inverse narrow width effect on sub-threshold device sizing and proposed a new sizing method to balance the rise and fall delay by taking into account the influence of inverse narrow width effect while minimizing the transistor size. Compared with the previous sub-threshold sizing method the delay and power-delay-product are reduced by up to 35.4% and 73.4% with up to 57% saving in the area. Further, due to symmetric rise and fall delay the minimum operating voltage can be lowered by 8% which leads to another 16% of energy reduction. |
| Slides |