| Title | A Polynomial-Time Custom Instruction Identification Algorithm Based on Dynamic Programming |
| Author | *Junwhan Ahn, Imyong Lee, Kiyoung Choi (Seoul National University, Republic of Korea) |
| Page | pp. 573 - 578 |
| Keyword | ASIPs, Configurable processors, Instruction-set extension, Dynamic programming |
| Abstract | This paper introduces an innovative algorithm for automatic instruction-set extension, which gives a pseudo-optimal solution within polynomial time to the size of a graph. The algorithm uses top-down dynamic programming strategy with the branch-and-bound algorithm in order to exploit overlapping of subproblems. Correctness of the algorithm is formally proved, and time complexity is analyzed from it. Also, it is verified that the algorithm gives an optimal solution for some type of merit functions, and has very small possibility of obtaining non-optimal solution in general. Furthermore, several experimental results are presented as evidence of the fact that the proposed algorithm has notable performance improvement. |
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| Title | Exploring the Fidelity-Efficiency Design Space using Imprecise Arithmetic |
| Author | *Jiawei Huang, John Lach (University of Virginia, U.S.A.) |
| Page | pp. 579 - 584 |
| Keyword | fidelity-efficiency tradeoffs, imprecise adders, reduced precision, Pareto frontier, CORDIC |
| Abstract | Recently many imprecise circuit design techniques have been proposed for implementation of error-tolerant applications, such as multimedia and communications. These algorithms do not mandate absolute correctness of their results, and imprecise circuit components can therefore leverage this relaxed fidelity requirement to provide performance and energy benefits. In this paper, several imprecise adder design techniques are classified and compared in terms of their error characteristics and power-delay efficiency. A general methodology for fidelity-efficiency design space exploration is presented and is applied to a case study implementing the CORDIC algorithm in 130nm technology. The case study reveals that simple precision scaling often provides better power-delay efficiency for a given fidelity than more complex imprecise adders, but different choice of algorithm and fidelity can influence the outcome. |
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| Title | Throughput Optimization for Latency-Insensitive System with Minimal Queue Insertion |
| Author | Juinn-Dar Huang, *Yi-Hang Chen, Ya-Chien Ho (National Chiao Tung University, Taiwan) |
| Page | pp. 585 - 590 |
| Keyword | Latency-Insensitive System, Latency-Insensitive-design, Throughput Optimization, Queue Size Minimization, Integer Linear Programming |
| Abstract | As fabrication process exploits even deeper submicron technology, global interconnect delay is becoming one of the most critical performance obstacles in system-on-chip (SoC) designs nowadays. Recent years latency-insensitive system (LIS), which enables multicycle communication to tolerate variant interconnect delay without substantially modifying pre-designed IP cores, has been proposed to conquer this issue. However, imbalanced interconnect latency and communication back-pressure residing in an LIS still degrade system throughput. In this paper, we present a throughput optimization technique with minimal queue insertion. We first model a given LIS as a quantitative graph (QG), which can be further compacted using the proposed techniques, so that much bigger problems can be handled. On top of QG, the optimal solution with minimal queue size can be achieved through integer linear programming based on the proposed constraint formulation in an acceptable runtime. The experimental results show that our approach can deal with moderately large systems in a reasonable runtime and save about 28% of queues compared to the prior art. |
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| Title | A Fast and Effective Dynamic Trace-based Method for Analyzing Architectural Performance |
| Author | *Yi-Siou Chen, Lih-Yih Chiou, Hsun-Hsiang Chang (Dept. of Electrical Engineering National Cheng Kung University, Taiwan) |
| Page | pp. 591 - 596 |
| Keyword | System analysis and design, Computer aided design, Space Exploration, Digital Systems |
| Abstract | Performance estimation at system-level involves quantitative analysis to allow designers to evaluate alternative architectures before implementation. However, designers must spend a tremendous amount of time in system remodeling for performance estimation for each alternative solution in a huge design space. The effort required for system remodeling prolongs the exploration step. Furthermore, the accuracy and speed of performance analysis affects the effectiveness of architectural exploration. This work presents an architectural performance analysis using a dynamic trace-based method (APDT) to reduce the effort required for system remodeling and the time required to estimate performance during architecture exploration, thereby improving the effectiveness of that exploration. Experimental results demonstrate that the APDT approach is faster than the bus functional-level simulation on CoWare with a minor average deviation. |
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