Title | Fault Simulation and Test Generation for Clock Delay Faults |
Author | *Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi (Ehime Univ., Japan), Kewal K. Saluja (Univ. of Wisconsin-Madison, U.S.A.) |
Page | pp. 799 - 805 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Compression-Aware Capture Power Reduction for At-Speed Testing |
Author | *Jia Li (Tsinghua Univ., China), Qiang Xu (Chinese Univ. of Hong Kong, Hong Kong), Dong Xiang (Tsinghua Univ., China) |
Page | pp. 806 - 811 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Fault Diagnosis Aware ATE Assisted Test Response Compaction |
Author | Joseph Howard, *Sudhakar M Reddy (Univ. of Iowa, U.S.A.), Irith Pomeranz (Purdue Univ., U.S.A.), Bernd Becker (Univ. of Freiburg, Germany) |
Page | pp. 812 - 817 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Secure Scan Design Using Shift Register Equivalents against Differential Behavior Attack |
Author | *Hideo Fujiwara (NAIST, Japan), Katsuya Fujiwara, Hideo Tamamoto (Akita Univ., Japan) |
Page | pp. 818 - 823 |
Detailed information (abstract, keywords, etc) | |
Slides |