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The 16th Asia and South Pacific Design Automation Conference

Session 9C  Clock and Package
Time: 16:00 - 18:00 Friday, January 28, 2011
Location: Room 414+415
Chair: Yasuhiro Takashima (Univ. of Kitakyushu, Japan)

9C-1 (Time: 16:00 - 16:30)
TitleAn Efficient Algorithm of Adjustable Delay Buffer Insertion for Clock Skew Minimization in Multiple Dynamic Supply Voltage Designs
AuthorKuan-Yu Lin, *Hong-Ting Lin, Tsung-Yi Ho (National Cheng Kung Univ., Taiwan)
Pagepp. 825 - 830
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9C-2 (Time: 16:30 - 17:00)
TitleAn Integer Programming Placement Approach to FPGA Clock Power Reduction
Author*Alireza Rakhshanfar, Jason Anderson (Univ. of Toronto, Canada)
Pagepp. 831 - 836
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9C-3 (Time: 17:00 - 17:30)
TitleRow-Based Area-Array I/O Design Planning in Concurrent Chip-Package Design Flow
AuthorRen-Jie Lee, *Hung-Ming Chen (National Chiao Tung Univ., Taiwan)
Pagepp. 837 - 842
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9C-4 (Time: 17:30 - 18:00)
TitleA Provably Good Approximation Algorithm for Rectangle Escape Problem with Application to PCB Routing
AuthorQiang Ma, Hui Kong, *Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.), Evangeline F. Y. Young (Chinese Univ. of Hong Kong, Hong Kong)
Pagepp. 843 - 848
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