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Session 5B: Power and Performance Optimization for Embedded Systems
5B-1 (Time: 13:30 - 13:55)
| Title |
Hybrid Solid-State Disks: Combining Heterogeneous NAND Flash in Large SSDs |
| Author |
*Li-Pin Chang (Nat’l Chiao Tung Univ., Taiwan) |
| Abstract |
This paper presents a hybrid approach to large SSDs. The idea is to complement the drawbacks of SLC flash and MLC flash with each other's advantages. The technical issues of the design of a hybrid SSD pertain to data placement and wear leveling over heterogeneous NAND flash. Our experimental results show that a hybrid SSD improves over a conventional SSD by 4.85 times in terms of average response. The average throughput and energy consumption are improved by 17% and 14%, respectively. |
| Slides |
5B-2 (Time: 13:55 - 14:20)
| Title |
Enabling Run-Time Memory Data Transfer Optimizations at the System Level with Automated Extraction of Embedded Software Metadata Information |
| Author |
*Alexandros Bartzas (Democritus Univ. of Thrace, Greece), Miguel Peon-Quiros (Universidad Complutense de Madrid, Spain), Stylianos Mamagkakis, Francky Catthoor (IMEC vzw, Belgium), Dimitrios Soudris (Democritus Univ. of Thrace, Greece), Jose Manuel Mendias (Universidad Complutense de Madrid, Spain) |
| Abstract |
The information about the run-time behavior of software applications is crucial for enabling system level optimizations for embedded systems. This embedded software Metadata information is especially important today, because several complex multi-threaded applications are mapped on the memory of a single embedded system. Each thread is triggered at run-time by different input events that can not be predicted at design-time. New methods and tools are needed to automatically profile and analyze the dynamic data access behavior of simultaneously executing threads in order to enable memory data transfer optimizations. In this paper, we propose such a method and tool which extract the necessary software Metadata information to enable these data transfer optimizations at the system level. We assess the effectiveness of our approach with the results for 5 real-life software applications using 7 real-life run-time input traces. |
| Slides |
5B-3 (Time: 14:20 - 14:45)
| Title |
Automatic Re-Coding of Reference Code into Structured and Analyzable SoC Models |
| Author |
Pramod Chandraiah, *Rainer Dömer (Univ. of California, Irvine, USA) |
| Abstract |
The quality of the input system model has a direct bearing on the effectiveness of the system exploration and synthesis tools. Given a well-structured system model, tools today are effective in generating efficient implementations. However, readily available reference C codes are not conducive for system synthesis as they lack the necessary structure and analyzability needed by the design flow. Usually reference C code is manually converted into a SoC model by applying necessary transformations. The type of transformations depends on the underlying design flow and tools. Proper structural hierarchy is one essential feature needed for architectural exploration. In this paper, we provide automatic C code transformations to encapsulate functions and insert structural hierarchy to create well-structured and analyzable SoC models. Our automatic transformations, combined with interactive application of the designer's knowledge and experience, enable faster creation of structural hierarchy in C models and hence result in significant reduction of the overall design time. |
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5B-4 (Time: 14:45 - 15:10)
| Title |
Action Coverage Formulation for Power Optimization in Body Sensor Networks |
| Author |
Hassan Ghasemzadeh, *Eric Guenterberg, Katherine Gilani, Roozbeh Jafari (Univ. of Texas, Dallas, USA) |
| Abstract |
Advances in technology have led to the development of various light-weight sensory devices that can be woven into the physical environment of our daily lives. Such systems enable on-body and mobile health-care monitoring. Our interest particularly lies in the area of movement monitoring platforms that operate with inertial sensors. In this paper, we propose a power optimization technique that will consider the sensing coverage problem from a collaborative signal processing perspective. We introduce compatibility graphs and describe how they can be utilized for power optimization. The problem we outline can be transformed into an NP-hard problem. Therefore, we propose an ILP formulation to attain a lower bound on the solution and a fast greedy technique. Along side this, we introduce a system for dynamically activating and deactivating sensor nodes in real-time. Finally, we elucidate the effectiveness of our techniques on data collected from several subjects. |
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5B-5 (Time: 15:10 - 15:23)
| Title |
Dynamic Scheduling of Imprecise-Computation Tasks in Maximizing QoS under Energy Constraints for Embedded Systems |
| Author |
*Heng Yu, Bharadwaj Veeravalli, Yajun Ha (Nat’l Univ. of Singapore, Singapore) |
| Abstract |
In designing energy-aware CPU scheduling algorithms for real-time embedded systems, dynamic slack reclamation techniques significantly improve system Quality-of-Service (QoS) and energy efficiency. However, the limited schemes in this domain either demand high complexity or can only achieve limited QoS. In this paper, we present a novel low complexity runtime scheduling algorithm for the Imprecise Computation (IC) modeled tasks. The target is to maximize system QoS under energy constraints. Our proposed algorithm, named Gradient Curve Shifting (GCS), is able to decide the best allocation of slack cycles arising at runtime, with very low complexity. We study both linear and concave QoS functions associated with IC modelde tasks, on non-DVS and DVS processors. Furthermore, we apply the intra-task DVS technique to tasks and achieve as large as 18% more of the system QoS compared to the conventional “optimal” solution which is inter-task DVS based. |
| Slides |
Last Updated on: January 31, 2008
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