Special Session

  • Date: January 19 - 21, 2010
  • Place: Taipei International Convention Center, 1F





Tuesday, January 19/

Techniques for Efficient Energy Harvesting and Generation for Portable and Embedded Systems


Tuesday, January 19/

3D Integration and Networks on Chips (Panel)


Wednesday, January 20/

Recent Advancement in Post-Silicon Validation


Thursday, January 21/

Dependable Silicon Design with Unreliable Components


Thursday, January 21/

ESL: Analysis and Synthesis of Multi-Core Systems

1D : Tuesday, January 19, 13:30-15:10, Room 101 D

Topic : Techniques for Efficient Energy Harvesting and Generation for Portable and Embedded Systems
Organizer & Chair: Pai Chou (Univ. of California, Irvine, USA/ National Tsing Hua Univ., Taiwan)

  • 1D-1: Room-Temperature Fuel Cells and Their Integration into Portable and Embedded Systems
    Authors: Naehyuck Chang, Jueun Seo, Donghwa Shin, and Younghyun Kim
    Affiliation of All Authors: Seoul National Univ., Republic of Korea
    Speaker: Naehyuck Chang
  • 1D-2: Maximizing the Harvested Energy for Micro-Power Applications through Efficient MPPT and PMU Design
    Authors: Hui Shao, Chi-ying Tsui, Wing-Hung Ki
    Affiliation of All Authors: Hong Kong Univ. of Science and Technology, Hong Kong
    Speaker: Chi-Ying Tsui
  • 1D-3: Dynamic Power Management in Environmentally Powered Systems
    Authors: Clemens Moser, Jian-Jia Chen, and Lothar Thiele
    Affiliation of All Authors: ETH Zurich
    Speaker: Jian-Jia Chen
  • 1D-4: Micro-scale energy harvesting: A system perspective
    Authors: Lu Chao, Vijay Raghunathan, and Kaushik Roy
    Affiliation of All Authors: Purdue Univ., USA
    Speaker: Vijay Raghunathan


2D : Tuesday, January 19, 15:30-17:10, Room 101 D

Panel Discussion : 3D Integration and Networks on Chips
Organizer & Moderator: Srinivasan Murali


Vertical stacking of multiple silicon layers, referred to as 3D stacking, is emerging as an attractive solution to continue the pace of growth of Systems on Chips (SoCs). 3D designs have a smaller footprint and shorter wires, leading to lower wire delay and power consumption. Heterogeneous systems can be built effectively, with each layer supporting a diverse technology. The 3D technology has been maturing over the years in addressing thermal issues and achieving high yield.
To tackle the on-chip communication problem, a scalable networking paradigm, Networks on Chips (NoCs) has recently emerged. NoCs provide better structure, modularity and scalability when compared to traditional interconnect solutions.
NoCs are a necessity for 3D chips: they provide arbitrary scalability of the interconnects across additional layers, efficiently parallelize communication in each layer and help controlling the number of vertical wires needed for inter-layer communication. The combined use of 3D integration technologies and NoCs introduces new opportunities and challenges for designers. In this panel, we will discuss the current state-of-the-art of 3D technologies and how NoC based solutions solve the interconnect problems. We will discuss the opportunities and challenges in adopting NoCs for 3D ICs.

Bios of Panelists:
Organizer & Moderator: Srinivasan Murali
Srinivasan Murali (iNoCs, EPFL) -- Moderator Srinivasan Murali is a co-founder and CTO of iNoCs. He also holds a research scientist position at EPFL. He received the MS and PhD degrees in Electrical Engineering from Stanford University in 2007. His research interests include interconnect design for Systems on Chips, with particular emphasis on developing CAD tools and design methods for Networks on Chips. His interests also include thermal modeling and reliability of multi-core systems. He is a recipient of the EDAA outstanding dissertation award for 2007 for his work on interconnect architecture design.

Ruchir Puri (IBM) --- Ruchir Puri received M.Tech. degree in electrical engineering from Indian Institute of Technology (IIT), Kanpur, India in 1990, and a Ph.D. degree in electrical and computer engineering from University of Calgary, Alberta, Canada in 1994 where he received 1993 ACM/IEEE Design Automation fellowship. He joined VLSI Design Automation group at IBM Thomas J. Watson Research Center, Yorktown Heights, NY in 1995, where he manages a research group focused on Logic and Physical Synthesis.

Paull Marchal (IMEC) -- Dr. Paul Marchal is presently Principal Scientist and Program Manager 3D design, IMEC, Belgium. In this function, he is responsible for developing design and test solutions enabling 3D integration technologies. Prior to this assignment, he worked at IMEC as Senior Research Engineer on design solution for advanced CMOS technologies. He graduated as Ph.D in Electrical Engineering, Catholic University of Leuven, Belgium in 2005 on memory optimization for multi-threaded applications.

Yuan Xie (Penn State) -- Yuan Xie is Associate Professor in Computer Science and Engineering department at the Pennsylvania State University. He received Ph.D. degree in electrical engineering from Princeton University. He was a recipient of NSF CAREER award in 2006, and IBM Faculty Award in 2008. He also received Best Paper Award in ASP-DAC 2008. He is a co-editor for a new book titled "3D ICs: Design, CAD, and Architecture", which will be published by Springer in Sept. 2009.

Ahmed Jerraya (LETI) -- Dr. Ahmed Jerraya is Director of Strategic Design Programs at CEA/LETI France. He served as General Chair for the Conference DATE in 2001, Co-founded MPSoC Forum (Multiprocessor system on chip) and is the organization chair of ESWEEK2009. He supervised 51 PhD, co-authored 8 Books and published more than 250 papers in International Conferences and Journals.

Nobuaki Miyakawa (Honda Research) – Nobuaki Miyakawa joined Honda R&D in 2001 and has been working on the development of process and design technology for 3D stacking devices at Honda Research Institute, Japan since 2003. His interests include display devices, optical detectors, mixed analogue and digital LSIs, multi-computer systems for the analysis of massive many-body problem and Brain-like computer. Miyakawa recieved the BS degree in Electrical Engineering from Muroran Institute of Technology, Muroran, Japan, in 1969.

3D : Wednesday, January 20, 08:30-10:10, Room 101 D

Topic : Recent Advancement in Post-Silicon Validation
Chair: Ing-Jer Huang (National Sun Yat-Sen University, Taiwan)

  • 3D-1: "Data learning based diagnosis"
    Author: Li-C. Wang (Univ. of California, Santa Barbara)
  • 3D-2: "Using Introspective Software-Based Testing for Post-Silicon Debug and Repair"
    Author: Todd Austin (Univ. of Michigan)
  • 3D-3: "Post-silicon debugging for multi-core designs";
    Author: Valeria Bertacco (Univ. of Michigan)
  • 3D-4: Low-Cost Repair Techniques by Using Partitioning
    Authors: Kyungho Kim, Byungtae Kang, Dongyun Kim (Samsung Electronics Co.), Sungchul Lee, Juyong Shin and Hyunchul Shin (Hanyang University)
  • 3D-5: "On Signal Tracing in Post-Silicon Validation"
    Author: Qiang Xu and Xiao Liu (The Chinese University of Hong Kong)

7D : Thursday, January 21, 08:30-10:10, Room 101 D

Topic : Dependable Silicon Design with Unreliable Components
Organizer & Moderator: Vincent Mooney, Georgia Tech and Nanyang Technological University

  • 7D-1: Resilient Design in Scaled CMOS for Energy Efficiency
    Author: Vivek De, Intel Corporation
  • 7D-2:  Benefits and Barriers to Probabilistic Design
    Author: Siva Narendra (Tyfone, Inc., U.S.A.)
  • 7D-3: A Probabilistic Boolean Logic for Energy Efficient Circuit and System Design
    Authors: Lakshmi N. B. Chakrapani (Rice Univ., U.S.A.), Krishna Palem (Rice Univ./Nanyang Technological Univ., U.S.A.)
  • 7D-4: (Panel Discussion) Dependable Silicon Design with Unreliable Components
    Organizer & Moderator: Vincent Mooney (Georgia Tech/Nanyang Technological Univ., U.S.A.)
    Panelists: Vivek K. De (Intel Corp., U.S.A.), Siva Narendra (Tyfone, Inc., U.S.A.), Krishna Palem (Rice Univ./Nanyang Technological Univ., U.S.A.)

8D : Thursday, January 21, 10:30-12:10, Room 101 D

Topic : ESL: Analysis and Synthesis of Multi-Core Systems
Organizer & Chair: Daniel D. Gajski, University of California at Irvine, USA

  • 8D-1: Computer-Aided Recoding for Multi-Core Systems
    Author: Rainer Dömer (University of California, Irvine, USA)
  • 8D-2: TLM Automation for Multi-core Design
    Author: Samar Abdi (Concordia University, Canada)
  • 8D-3: Platform Modeling for Exploration and Synthesis
    Authors: Andreas Gerstlauer (University of Texas at Austin, USA)
    Gunar Schirner (Northeastern University, Boston, USA)
  • 8D-4: ESL Synthesis and Verification
    Author: Alan Su (Global Unichip, Taiwan)