• Date: Monday, January 18, 2010 (9:30 - 17:00)
  • Place: Taipei International Convention Center , 1F
Time Title
Tutorial 1 (Half Day) 9:30 - 12:30 Embedded Software for System-on-Chip (SoC) Design
Tutorial 2 (Half Day) 14:00 - 17:00 Analog and Mixed-signal Circuit Design in Nanometer CMOS Technologies
Tutorial 3 (Full Day) 9:30 - 12:30 , 14:00 - 17:00 3D Integrated Circuit Design
Tutorial 4  (Full Day) 9:30 - 12:30 , 14:00 - 17:00 Industrial Low-Power Circuit Design
Tutorial 5 (Full Day) 9:30 - 12:30 , 14:00 - 17:00 The Convergence and Inter-relationship of Yield, Design for Manufacturability and Test

Tutorial 1 (Half DAY), Monday, January 18, 9:30 - 12:30, Room 101 A

Embedded Software for System-on-Chip (SoC) Design

Tie-Wei Kuo (National Taiwan University, Taiwan)
Lothar Thiele (Swiss Federal Institute of Technology (ETH) , Switzerland)
Tie-Wei Kuo (National Taiwan University, Taiwan)

Tutorial Summary:

1.Embedded Software Design for Multiprocessor System-on-Chip (MPSoC)
For many emerging embedded applications, high performance is required: High-quality multimedia processing in consumer electronics, software defined radio in communications systems, or real-time diagnostics in medical systems are typical examples. A frequent choice for digital signal processing systems will be heterogeneous multiprocessor system-on-chip (MPSoCs) because of their computational power, programmability, and low power dissipation.
Software development plays a central role in handling the increasing complexity of applications implemented on MPSoCs. Productively programming heterogeneous MPSoCs requires support for concurrency, timing, heterogeneity, scalability, and hardware/software system integration. This support is only provided to a very limited degree by the traditional practice of using C/C++ and a board support package to program single and multiprocessor signal processing systems.
Recognizing this challenge, a variety of techniques and complete software design flows have been proposed that shift the software development for MPSoCs to higher levels of abstraction. In those design flows, applications are developed using a high-level application programming interface (API), or a model of computation. These approaches attempt to assist software developers in the necessary high-level design decisions and allow automating certain steps in the design flow.
A particular challenge is the performance analysis of MPSoCs which is required for early design space exploration and final system verification. Simulation-based methods are not well suited for this purpose due to long run-times and missing corner-case coverage. To overcome these limitations, formal performance analysis methods that scale to large systems and provide guarantees for meeting real-time constraints have been developed. Embedding formal performance analysis into the MPSoC design cycle requires the generation of a faithful analysis model and its calibration with the system-specific parameters.
The tutorial will provide an overview about the major challenges in multiprocessor software development. We will present a taxonomy of software design flows based on this analysis, review current MPSoC software design flows and classify them based on the associated challenges. As an example, a design flow is presented that integrates a modular performance analysis method into the MPSoC programming environment. The result is an MPSoC software design flow that allows to automatically generate the system implementation together with an analysis model for system verification.

2.The Design and Implementation Issues of Flash-Memory Storage Systems
While flash memory has been widely adopted in the implementations of various storage systems, it recently receives a lot of attention in various system-component designs. With the unique characteristics of flash memory, it is highly challenging in the designs of management software, especially when reliability and performance become major concerns. In this tutorial, we will summarize popular implementations of the management software, and the behavior analysis of flash-memory storage systems will also be addressed. Challenge issues for current and future implementations, especially on reliability and file-system considerations, and some potential solutions will be presented.

Tutorial 2 (Half DAY), Monday, January 18, 14:00 - 17:00, Room 101 A

Analog and Mixed-signal Circuit Design in Nanometer CMOS Technologies

Organizer & Speaker:
Georges Gielen (Katholieke Universiteit Leuven, Belgium)
Tutorial Summary:
Nanometer CMOS technologies pose particular challenges to the design of analog and mixed-signal integrated circuits. This tutorial will discuss design techniques to overcome these challenges and will illustrate this with several practical design examples. Examples given include ultra-low-power design, design for reliability, reconfigurable designs, etc.

Tutorial 3 (Full DAY), Monday, January 18, 9:30 - 17:00, Room 101 B

3D Integrated Circuit Design

Sachin Sapatnekar (ECE Dept., University of Minnesota , USA)
Paul Franzon (ECE Dept., North Carolina State University, USA)
Ruchir Puri (IBM TJ Watson Research Center, USA)
Sachin Sapatnekar (ECE Dept., University of Minnesota , USA)
Yuan Xie (CSE Dept., Pennsylvania State University, USA)
Tutorial Summary:
Despite generation upon generation of technology scaling, computer chips have remained essentially two-dimensional (2D). Improvements in the on-chip wire delay, and in the maximum number of inputs and outputs per chip have not been able to keep up with transistor performance growth, and it has become progressively harder to hide the discrepancy. In contrast with these conventional 2D circuits, 3D integrated circuits offer a new paradigm that builds multiple tiers of active devices stacked above each other. Recent advances in process technology have brought 3D technology to the point where it is feasible and practical, and it has raised widespread interest in the chip industry. The move to 3D allows numerous benefits over 2D, such as reduced interconnect lengths, improved computation per unit volume, and the possibility of integrating heterogeneous systems. However, the paradigm requires a significant change from contemporary design methodologies, since an optimal 3D chip design has very different characteristics from an optimal 2D chip design. The goal of this tutorial is to provide an overview of the technology, the corresponding design challenges, and existing solutions to overcome these challenges.
3D chip technologies come in a number of flavors that are expected to enable the extension of CMOS performance. Designing in 3D forces the industry to look at formerly-two-dimensional integration issues quite differently, and requires the re-fitting of multiple existing EDA capabilities. We begin with an overview of the motivation for 3D, process steps, and delve into the design issues in detail.
We then address how the technology can be used to provide significant performance benefits: up to now 3DIC technologies, through silicon vias (TSV), and bonding techniques, have mainly been exploited in view of their potential for miniaturization. However, the open question is how to exploit 3DIC for reasons beyond just size and weight. It is becoming clear that if the system is re-architected to explicitly account for 3D IC technology, advantages can be gained in performance, power consumption, and cost. However, complicating factors that must be dealt with include partitioning, design management, thermal design, and manufacturing test.
A key part of the 3D solution lies in the development of EDA solutions to address such 3D-specific issues, and the next part of the tutorial overviews the specific role for new computer-aided design (CAD) tools that can solve problems related to building designs in 3D: specifically, 3D physical design, thermal management, and power delivery. We will also discuss how one can extend the existing 2D design flows to adapt to 3D as opposed to inventing new flows. Design flow steps unique to 3D will also be described.
Finally, the tutorial will address architectural issues in 3D design. Design space exploration at the architectural level is essential to fully take advantage of the 3D integration technologies and to build high performance microprocessors. In this tutorial, we will discuss fine-granularity and coarse-granularity processor design options, and present various novel architecture designs enabled by 3D integration, leveraging the benefits of faster and high-bandwidth communication to stacked layer, as well as the heterogeneous integration capability.

Tutorial 4(Full DAY), Monday, January 18, 9:30 - 17:00, Room 101 C

Industrial Low-Power Circuit Design

Pei-Hsin Ho (Synopsys Inc., USA)
Louis Jiing-Yuan Lin (Global Unichip Corporation, Taiwan)
Yoshio Inoue (Renesas Technology Corporation, Japan)
David Flynn (ARM Ltd, UK)
Pei-Hsin Ho (Synopsys Inc., USA)

Tutorial Summary:
Power consumption is the primary concern for almost all IC designs --- whether they target consumer electronics or high-performance computers. In this tutorial, world-class experts will illustrate state-of-the-art low-power design techniques and share silicon-proven design experiences that practitioners as well as researchers in low-power design may find useful and insightful. In particular, the tutorial will cover details of leakage power minimization through power gating, including discussions of (1) in-rush current and dynamic IR drop analysis, (2) power switch placement and stitching, (3) state retention overhead minimization and reliability analysis, (4) power-gating testability and (5) implementing low-power SoCs using EDA tools that support UPF or CPF. The tutorial will also cover details of dynamic power minimization through multiple power domain design and advanced low-power System, RTL and physical design, including discussions of (1) multi-Vdd designs, (2) DVFS (Dynamic Voltage and Frequency Scaling) implementation and verification, (3) multi-depth sleep mode, (4) low-power clock-tree synthesis and (5) low-power asynchronous design. The speakers will also discuss their hands-on experiences in 65nm technologies, large low-power SoCs, designs with 50 power modes, power gating using PMK (power management kits) and ARM1176JZF-S processor.

Tutorial Outline

  1. Physical Implementation and Verification of Multiple Power Domain Designs by Jiing-Yuan Lin: Discuss technical challenges of power gating designs and share physical implementation and verification experiences on those designs, especially in power switch placement and stitching, rush current and dynamic IR analysis, state retention, and the handling of complicated designs with over 50 power domains and power modes. In practice, one may employ multi-supply voltage or dynamic voltage and frequency scaling (DVFS) techniques accompanied with power gating and multi-depth sleep modes to reduce both dynamic and leakage power consumption. This tutorial also covers our experiences of DVFS implementation and verification.
  2. Low-Power SoC Design Issues and Solutions by Yoshio Inoue: The market demands ever more functionalities in a single system at a lower cost. As a result, Renesas Technology designed many large-scale SoC chips implemented using advanced low power design solutions. But today’s low-power design solutions are expensive and difficult to implement, even with state-of-the-art EDA tools that support UPF or CPF. Many improvements in the EDA tools are still needed in many key areas of the low-power design process. This tutorial will discuss key issues in the chip implementation flow and how these issues may be resolved using improved in-house and commercial EDA tools.
  3. Practical Low-Power Design at 65nm - Case Study and Analysis by David Flynn: The research group at ARM has worked for a number of years with customers and leading EDA partners to take complex 'expert' low-power industry techniques and facilitate their successful adoption for standard System-on-Chip designers and implementers. We will present the work on the latest technology demonstrator at 65nm and compare and contrast the dynamic and static leakage power minimization approaches applied to an ARM1176JZF-S processor together with the measured silicon results. In particular, we will discuss power gating using "PMK" power management kits, inrush current turn-on management for fast wake-up, testability approaches for power gating, state Retention integrity and reliability, and novel approaches to reduce state retention area overheads. The tutorial covers what matters from the system and RTL designer perspective, and provides an in-depth view of the realizable power savings and verification implications.
  4. Low-Power Design Techniques by Pei-Hsin Ho: We introduce (1) low-power CTS and placement techniques, (2) low-power design IPs and (3) low-power asynchronous design methodology in this tutorial.

Tutorial 5 (Full DAY), Monday, January 18, 9:30 - 17:00, Room 101 D

The Convergence and Inter-relationship of Yield, Design for Manufacturability and Test

Srikanth Venkataraman (Intel Corporation , USA)
Srikanth Venkataraman (Intel Corporation , USA)
Robert C. Aitken (ARM Ltd, USA)
Tutorial Summary:
The tutorial goal is to how how design for yield (DFY) and design for manufacturability (DFM) are tightly coupled into what we conventionally think of as test. As process geometries shrink, the line between defects and process variation blurs to the point where it is essentially non-existent. As feature sizes reduced to 90 nm micron and below, systematic mechanism-limited yield loss began to appear as a substantial component in yield loss due to the interaction between design and manufacturing. The basics of yield and what fabs do to improve defectivity and manage yield are described. DFM techniques to analyze the design content, flag areas of design that could limit yield, and make changes to improve yield are discussed. In DFM/DFY circles, it is common to speak of defect limited yield, but it is less common to think of test-limited yield, yet this concept is common in DFT (e.g. IDDQ testing, delay testing). Test techniques to close the loop by crafting test patterns to expose the defect prone feature and circuit marginality through ATPG, and by analyzing silicon failures through diagnosis to determine the features that are actually causing yield loss and their relative impact are covered. This tutorial will provide background needed for DFT practitioners to understand DFM and DFY, and see how their work relates to it. The ultimate goal is to spur attendees to conducting their own research in the area, and to apply these concepts in their jobs.

Tutorial Outline

Section 1: Introduction and background (30 mins)
  • Introduction
  • Tutorial goal
  • What is Yield?
  • What is DFX? Interaction of manufacturability, yield, variability, and test
Section 2: Yield and Fab Metrology (60 mins)
  • Manufacturability versus yield
  • Sources of Yield loss – Random, Systematic and Parametric, Defect versus design-related
  • Yield models and metrics: Poisson, negative binomial, Murphy,
  • Economics of yield
  • Redundancy/Repair: Memory and logic
  • How does a Fab improve defectivity and manage yield? Fab Metrology, In-line inspections, Process control, Test chips and test structures, SRAM-based, feature-based, ring oscillators, Yield management systems (YMS)
Section 3: DFM - Design for Manufacturability(90 mins)
  • What is DFM?
  • Lithography: DRC rules, recommendations, shape-based effects, process window, simulation
  • Resolution Enhancement Techniques (RET): Optical proximity correction (OPC), Phase shift mask (PSM), Sub resolution assist features (SRAF), Off axis illumination (OAI)
  • Chemical Mechanical Polishing (CMP): CMP modeling and analysis, density rules, dummy metal fill, systematic versus random components
  • Random defects and Critical Area Analysis (CAA): Shorts / opens / vias / contacts, inductive fault analysis, tradeoffs, optimization,
  • DRCs and DFM Guidelines
  • DFM Enhancement Techniques
  • Tradeoffs - Metrics, competing effects, the challenge of yield, design intent


Section 4: Variability (60 mins)
  • Design margin versus characterization
  • Statistical behavior - Timing models, path-based, block-based
  • Extreme value theory
  • Variability and parametric yield: Device, interconnect and environmental variations, Statistical design optimization


Section 5: DFT / Test and the link to Manufacturability and Yield (45 mins)
  • Variability and defects - Small delay defects
  • Correlation, test, and measurement
  • The relationship between test and yield
  • The relationship of DFT / Test to DFM
  • Test as the vehicle for product based silicon learning: Manufacturing and Defect aware tests, DFM-oriented tests,Timing aware tests


Section 6: Diagnosis and the feedback loop(45 mins)
  • Basics of logic, scan chain and memory diagnosis
  • Diagnosis of Delay Faults and Timing Errors
  • Defect learning from test and diagnosis
  • Memory diagnosis for yield improvement – bit-mapping
  • High-volume statistical diagnosis for yield learning - Statistical analysis and computation of defect rates; Providing feedback to DFM


Section 7: Putting it all together (30 mins)
  • Applying these techniques in your organization
  • What works and what doesn't
  • Areas for future research