University LSI Design Contest
The University LSI Design Contest was conceived as a unique program of
ASP-DAC Conference. The purpose of the Contest is to encourage education and
research in LSI design, and its realization on chips at universities, and
other educational organizations by providing opportunities to present and
discuss innovative and state-of- the-art designs at the conference.
Application areas and types of circuits include:
(1) Analog, RF and
Mixed-Signal Circuits,
(2) Digital Signal processing,
(3) Microprocessors,
and
(4) Custom Application Specific Circuits and Memories.
Methods or
technology used for implementation include:
(a) Full Custom and Cell-Based LSIs,
(b) Gate Arrays, and
(c) Field Programmable Devices, including FPGA/PLDs.
This year, 20 selected designs from six countries/areas will be disclosed in
Session 4D with a short presentation followed by live discussions in front
of posters with light meals. Submitted designs were reviewed by the members
of the University Design Contest Committee. As a result, the 20 designs were
selected. Also, we have instituted one outstanding design award from the
selected designs.
It is with great pleasure that we acknowledge the contributions to the Design Contest, and it is our earnest belief that it will promote and enhance research and education in LSI design in academic organizations. It is also our hope that many people not only in academia but in industry will attend the contest and enjoy the stimulating discussions.
- Date: Wednesday, January 20, 2010
- Place: Taipei International Convention Center, 1F
1) Oral Presentation : Room 101D (10:30-12:10)
2) Poster Presentation : Room 103 [Food will be served] (12:10-13:30) - Chair: Prof. Jiun-In Guo (National Chung Cheng University, Taiwan)
- Co-chairs : Prof. Masanori Hariyama (Tohoku University, Japan)
- University LSI design contest committee
- Poster Preparation Guidelines for University LSI Design Contest
|
Time |
Title |
10:30 - 10:35 |
Checker-Pattern and Shared Two Pixels LOFIC CMOS Image Sensors |
|
10:35 - 10:40 |
A CMOS Image Sensor With 2.0-e- Random Noise and 110-ke- Full Well Capacity Using Column Source Follower Readout Circuits |
|
10:40 - 10:45 |
Checkered White-RGB Color LOFIC CMOS Image Sensor |
|
10:45 - 10:50 |
A Versatile Recognition Processor for Sensor Network Applications |
|
10:50 - 10:55 |
A 2-6 GHz Fully Integrated Tunable CMOS Power Amplifier for Multi-Standard Transmitters |
|
10:55 - 11:00 |
An Embedded Debugging/Performance Monitoring Engine for a Tile-based 3D Graphics SoC Development |
|
11:00 - 11:05 |
Cascaded Time Difference Amplifier using Differential Logic Delay Cell |
|
11:05 - 11:10 |
Built-in Self At-Speed Delay Binning and Calibration Mechanism in Wireless Test Platform |
|
11:10 - 11:15 |
Dynamic Voltage Domain Assignment Technique for Low Power Performance Manageable Cell Based Design |
|
11:15 - 11:20 |
Adaptive Performance Control with Embedded Timing Error Predictive Sensors for Subthreshold Circuits |
|
11:20 - 11:25 |
A 60GHz Direct-Conversion Transmitter in 65nm CMOS Technology |
|
11:25 - 11:30 |
An Electrically Adjustable 3-Terminal Regulator with Post-Fabrication Level-Trimming Function |
|
11:30 - 11:35 |
Fine Resolution Double Edge Clipping with Calibration Technique for Built-In At-Speed Delay Testing |
|
11:35 - 11:40 |
Geyser-1: A MIPS R300 CPU core with fine-grained run-time Power Gating |
|
11:40 - 11:45 |
A WiMAX Turbo Decoder with Tailbiting BIP Architecture |
|
11:45 - 11:50 |
Temporal Circuit Partitioning for a 90nm CMOS Multi-Context FPGA and its Delay Measurement |
|
11:50 - 11:55 |
Design and Chip Implementation of an Instruction Scheduling Free Ubiquitous Processor |
|
11:55 - 12:00 |
MUCCRA-3: A Low Power Dynamically Reconfigurable Processor Array |
|
12:00 - 12:05 |
Rapid Prototyping on a Structured ASIC Fabric |
|
12:05 – 12:10 |
A High Performance Low Complexity Joint Transceiver for Closed-Loop MIMO Applications |