| Title | Allocation of FPGA DSP-Macros in Multi-Process High-Level Synthesis Systems |
| Author | *Benjamin Carrion Schafer (Hong Kong Polytechnic Univ., Hong Kong) |
| Page | pp. 616 - 621 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | Array Scalarization in High Level Synthesis |
| Author | Preeti Ranjan Panda, *Namita Sharma (Indian Inst. of Tech. Delhi, India), Arun Kumar Pilania, Gummidipudi Krishnaiah, Sreenivas Subramoney, Ashok Jagannathan (Intel Technology India Pvt., India) |
| Page | pp. 622 - 627 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | Data Compression via Logic Synthesis |
| Author | *Luca Amaru, Pierre-Emmanuel Gaillardon (EPFL-LSI, Switzerland), Andreas Burg (EPFL-TCL, Switzerland), Giovanni De Micheli (EPFL-LSI, Switzerland) |
| Page | pp. 628 - 633 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | Synthesis of Power- and Area-Efficient Binary Machines for Incompletely Specified Sequences |
| Author | *Nan Li, Elena Dubrova (Royal Inst. of Tech., Sweden) |
| Page | pp. 634 - 639 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | Multi-Mode Trace Signal Selection for Post-Silicon Debug |
| Author | *Min Li, Azadeh Davoodi (Univ. of Wisconsin - Madison, U.S.A.) |
| Page | pp. 640 - 645 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |